LOW SKEW, 1-TO-9
LVCMOS / LVTTL CLOCK MULTIPLIER
87950I DATA SHEET
8 REVISION C 11/6/15
FIGURE 2. CRYSTAL INPUT INTERFACE
CRYSTAL INPUT INTERFACE
The 87950I has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
These same capacitor values will tune any 18pF parallel res-
onant crystal over the frequency range and other parameters
specifi ed in this data sheet. The optimum C1 and C2 values can
be slightly adjusted for different board layouts.
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The 87950I provides separate
power supplies to isolate any high switching noise from the
outputs to the internal PLL. V
DDO
and V
DDA
should be individually
connected to the power supply plane through vias, and bypass
capacitors should be used for each pin. To achieve optimum
jitter performance, power supply isolation is required. Figure 1
illustrates how a 10Ω resistor along with a 10μF and a .01μF
bypass capacitor should be connected to each V
DDA
pin.
POWER SUPPLY FILTERING T ECHNIQUES
FIGURE 1. POWER SUPPLY FILTERING
10Ω
V
DDA
10μF
.01μF
3.3V
.01μF
V
DDO
APPLICATION INFORMATION
ICS84332
XTAL_IN
XTAL_OUT
X1
18pF Parallel Cry stal
C2
22p
C1
22p
