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UBA2015T/1,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42
UBA2016A_15_15A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 16 November 2011 7 of 42
NXP Semiconductors
UBA2016A/15/15A
600 V fluorescent lamp driver
7.2.1 Regulation loop
The control loop senses the PFC output voltage via resistors R1, R2 and the feedback
input FBPFC. The frequency compensation network C1, C2 and R4 sets the response
time and stability of the loop. The voltage at pin FBPFC is regulated to V
reg(FBPFC)
. When
voltage on pin FBPFC is above the regulation voltage, pin COMPPFC is charged and
when voltage on pin FBPFC is lower, pin COMPPFC is discharged. Current flow through
pin COMPPFC is controlled by the PFC Operational Transconductance Amplifier (OTA)
and its transconductance g
m(PFC)
. The voltage on pin COMPPFC controls the PFC
on-time, t
on(PFC)
. So when the voltage at pin FBPFC is too high, t
on(PFC)
is reduced and
less energy is transferred. When voltage at pin FBPFC is too low, t
on(PFC)
is increased and
more energy is transferred.
The voltage on pin FBPFC is sampled at the rising edge of pin GPFC and held internally
during the leading edge blanking time t
leb(FBPPC)
before going to the OTA to prevent
disturbance of the regulation level due to transition effects when the PFC external power
switch is turned on
The maximum t
on(PFC)
is set when the voltage at pin COMPPFC is clamped to
V
clamp(COMPPFC)
to limit the dead time in recovering regulation after a regulation range
overshoot. The t
on(PFC)
time can be regulated down to zero. The moment at which the
gate is turned on is determined by pin AUXPFC. When this pin is below demagnetization
detection voltage V
det(demag)AUXPFC
and the low PFC off-time t
off(PFC)low
timer is finished,
the next cycle starts.
During start-up, the capacitor connected to pin COMPPFC is connected by an internal
switch to pin FBPFC which allows it to partially charge before the PFC starts. This reduces
the start-up time.
Fig 6. Basic PFC application diagram
GND
VDD
FBPFCGPFC
AUXPFC
COMPPFC
V
o(PFC)
V
DSRmains
l
i(PFC)
l
o(PFC)
D
PFC
L
PFC
mains
Q
PFC
I
switch(PFC)
D
bypass
C
BUS
R1
R2
R4
C2
C1
R3
001aam533
UBA2016A
UBA2015
UBA2015A
UBA2016A_15_15A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 16 November 2011 8 of 42
NXP Semiconductors
UBA2016A/15/15A
600 V fluorescent lamp driver
7.2.2 Protection
The PFC incorporates the following protection mechanisms:
• When voltage on pin FBPFC drops below open/short protection threshold voltage
V
th(osp)(FBPFC)
, the gate is turned off and the start of a new cycle is inhibited. A small
internal filter prevents this protection reacting to a negative spike.
• When pin FBPFC is left open, a pull-down bias current I
bias(FBPFC)
ensures that the pin
voltage drops below V
th(osp)(FBPFC)
.
• When voltage at pin FBPFC rises above overvoltage threshold voltage V
th(ov)(FBPFC)
the gate immediately turns off. A new cycle will not start while V
FBPFC
remains above
V
th(ov)(FBPFC)
. This limits the PFC output voltage. This protection is disabled during the
leading edge blanking time t
leb(FBPFC)
after GPFC goes high.
• When the t
off(PFC)low
timer sequence has ended with no demagnetization detected
(V
AUXPFC
has not risen above V
det(demag)
) the on-time of the next cycle will be the no
demagnetization detected PFC on-time t
on(PFC)nodemag
to prevent excessive current
build up in the coil.
• Bias current I
bias(AUXPFC)
ensures that pin AUXPFC is HIGH when not connected
ensuring pin GPFC stays LOW.
7.3 Half-bridge driver
The IC incorporates drivers for the half-bridge switches and all related circuits such as
non-overlap, high voltage level shifter, bootstrap circuit for the floating supply and hard
switching and capacitive mode detection.
The UBA2016A/15/15A is designed to drive a half-bridge inverter with an inductive load.
The load consists typically of an inductor with a resonant capacitor and a TL or CFL. A
basic half-bridge application circuit driving a TL is shown in Figure 7
which also shows a
typical IC supply configuration with a start-up bleeder resistor and a dV/dt supply.
Fig 7. Basic half-bridge and IC supply connection diagram
V
BUS
UBA2016A
UBA2015
UBA2015A
VDD
GND
GHHB
SHHB
FSHB
GLHB
001aam534
UBA2016A_15_15A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 16 November 2011 9 of 42
NXP Semiconductors
UBA2016A/15/15A
600 V fluorescent lamp driver
7.3.1 VDD supply
The UBA2016A/15/15A is intended to be supplied by a start-up bleeder resistor
connected between the bus voltage V
BUS
and VDD and a dV/dt supply from the
half-bridge point at pin SHHB.
The IC starts up when the voltage at pin VDD rises above start-up voltage V
startup(VDD)
and
locks out (stops oscillating) when the voltage at pin VDD drops below stop voltage
V
stop(VDD)
. The hysteresis between the start and stop levels allows the IC to be supplied
by a buffer capacitor until the dV/dt supply is settled. The UBA2016A/15/15A has an
internal VDD clamp. This is an internal active Zener (or shunt regulator) that limits the
voltage on the VDD supply pin to clamp voltage V
clamp(VDD)
. No external Zener diode is
needed in the dV/dt supply circuit if the maximum current of the dV/dt supply minus the
current consumption of the IC (mainly determined by the gate drivers’ load) is below
I
clamp(VDD)
.
7.3.2 Low- and high-side drivers
The low- and high-side drivers are identical. The output of each driver is connected to the
equivalent gate of an external power MOSFET. The high-side driver is supplied by the
bootstrap capacitor, which is charged from the VDD supply voltage via an internal diode
when the low-side power MOSFET is on. The low-side driver is directly supplied by the
VDD supply voltage.
7.3.3 Non-overlap
During each transition between the two states GLHB HIGH/GHHB LOW and
GLHB LOW/GHHB HIGH, GLHB and GHHB will both be LOW for a fixed non-overlap time
t
no
to allow the half-bridge point to be charged or discharged by the load current
(assuming the load always has an inductive behavior), and enabling zero voltage
switching; see Figure 8
.
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UBA2015T/1,118

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Buy UBA2015T/1,118
Manufacturer:
NXP Semiconductors
Description:
Display Drivers & Controllers 600V 0.16mA SO20
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New from this manufacturer.
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