Device operation M34D64-W
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3.12 Current Address Read
The device has an internal address counter which is incremented each time a byte is read.
For the Current Address Read operation, following a Start condition, the bus master only
sends a Device Select Code with the Read/Write
bit (RW) set to 1. The device
acknowledges this, and outputs the byte addressed by the internal address counter. The
counter is then incremented. The bus master terminates the transfer with a Stop condition,
as shown in Figure 9.: Read mode sequences, without acknowledging the byte.
3.13 Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 9.: Read mode sequences.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory address
00h.
3.14 Acknowledge in Read mode
For all Read commands, the device waits, after each byte read, for an acknowledgment
during the 9
th
bit time. If the bus master does not drive Serial Data (SDA) low during this
time, the device terminates the data transfer and switches to its Standby mode.
