M34D64-WMN6P Datasheet M34D64-WMN6P, M34D64-WMN6T, M34D64-WMN6TP | P4-P6

List of tables M34D64-W

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List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 3. Most significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 4. Least significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 5. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 7. Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 8. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 9. Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 10. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 11. AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 12. SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data . . . . . . . . . . . 24

Table 13. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 14. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

M34D64-W List of figures

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List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. Memory map showing write control area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5. Maximum R

value versus bus capacitance (C

BUS

) for an I

C bus . . . . . . . . . . . . . . . . . . 10

Figure 6. I

C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 7. Write mode sequences with WC

= 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 8. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 9. Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 10. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 11. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 12. SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 24

Description M34D64-W

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1 Description

The M34D64-W are I

C-compatible electrically erasable programmable memory (EEPROM)

devices organized as 8192 x 8 bits.

These devices are compatible with the I

C memory protocol. This is a two-wire serial

interface that uses a bidirectional databus and serial clock. The devices carry a built-in 4-bit

Device Type Identifier code (1010) in accordance with the I

C bus definition.

The device behaves as a slave in the I

C protocol, with all memory operations synchronized

by the serial clock. Read and Write operations are initiated by a Start condition, generated

by the bus master. The Start condition is followed by a Device Select Code and Read/Write

bit (RW

) (as described in Table 2.: Device select code), terminated by an acknowledge bit.

When writing data to the memory, the device inserts an acknowledge bit during the 9

bit

time, following the bus master’s 8-bit transmission. When data is read by the bus master, the

bus master acknowledges the receipt of the data byte in the same way. Data transfers are

terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.

Figure 1. Logic diagram

Table 1. Signal names

Signal name Function Direction

E0, E1, E2 Chip Enable Input

SDA Serial Data I/O

SCL Serial Clock Input

Write Control Input

Supply voltage

Ground

AI02850c

E0-E2 SDA

M34D64-W

SCL

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27

M34D64-WMN6P

Mfr. #:

Buy M34D64-WMN6P

Manufacturer:

STMicroelectronics

Description:

EEPROM 64Kbit Serial EE

Lifecycle:

New from this manufacturer.

Delivery:

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M34D64-WMN6P

M34D64-WMN6P

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