932SQ428AKLFT Datasheet 932SQ428AKLF, 932SQ428AKLFT | P13-P15

932SQ428

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS

IDT®

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 13

932SQ428 REV E 042312

SMBus Table: Output Enable Register

Pin # Name Control Function Type 0 1 Defaul

t

Bit 7

DOT96 Enable Output Enable RW Disable-Hi-Z Enable 1

Bit 6

NS_SAS1 Enable Output Enable RW Disable-Hi-Z Enable 1

Bit 5

1

Bit 4

NS_SAS0 Enable Output Enable RW Disable-Hi-Z Enable 1

Bit 3

1

Bit 2

SRC2 Enable Output Enable RW Disable-Hi-Z Enable 1

Bit 1

SRC1 Enable Output Enable RW Disable-Hi-Z Enable 1

Bit 0

SRC0 Enable Output Enable RW Disable-Hi-Z Enable 1

SMBus Table: Output Enable Register

Pin # Name Control Function T

y

pe 0 1 Defaul

t

Bit 7

REF14_3x Enable Output Enable RW Disable-Low Enable 1

Bit 6

0

Bit 5

0

Bit 4

1

Bit 3

1

Bit 2

1

Bit 1

1

Bit 0

Spread Spectrum Enable Spread Off/On RW Spread Off Spread On 0

SMBus Table: Output Enable Re

g

ister

Pin # Name Control Function T

y

pe 0 1 Defaul

t

Bit 7

0

Bit 6

0

Bit 5

PCI4 Enable Output Enable RW Disable-Low Enable 1

Bit 4

PCI3 Enable Output Enable RW Disable-Low Enable 1

Bit 3

PCI2 Enable Output Enable RW Disable-Low Enable 1

Bit 2

PCI1 Enable Output Enable RW Disable-Low Enable 1

Bit 1

PCI0 Enable Output Enable RW Disable-Low Enable 1

Bit 0

48MHz Enable Output Enable RW Disable-Low Enable 1

Byte 3 ~ Byte 4 Reserved Register

SMBus Table: NS_SAS Frequenc

y

Mar

g

inin

g

Table

Pin # Name Control Function T

y

pe 0 1 Defaul

t

Bit 7

0

Bit 6

0

Bit 5

0

Bit 4

FS4 Fre

q

. Sel 4 R

W

0

Bit 3

FS3

Fre

q

. Sel 3 R

W

1

Bit 2

FS2

Fre

q

. Sel 2 R

W

1

Bit 1

FS1

Fre

q

. Sel 1 R

W

1

Bit 0

FS0 Freq. Sel 0 RW 1

SMBus Table: SRC/PCI Frequency Select Register

Pin # Name Control Function T

y

pe 0 1 Defaul

t

Bit 7

0

Bit 6

0

Bit 5

0

Bit 4

1

Bit 3

FS3 Freq. Sel 3 RW 1

Bit 2

FS2 Freq. Sel 2 RW 0

Bit 1

FS1 Freq. Sel 1 RW 0

Bit 0

FS0 Freq. Sel 0 RW 0

-

RESERVED

Byte 0

-

SRC/PCI

Byte 2

Byte 1

-

RESERVED

-

Byte 5

RESERVED

-

RESERVED

-

See NS_SAS Frequency Table

-

Byte 6

-

See SRC/PCI Frequency

Select Table

-

RESERVED

932SQ428

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS

IDT®

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 14

932SQ428 REV E 042312

SMBus Table: Vendor & Revision ID Register

Pin # Name Control Function Type 0 1 Default

Bit 7

RID3 R 0

Bit 6

RID2 R 0

Bit 5

RID1 R 1

Bit 4

RID0 R 1

Bit 3

VID 3 R 0

Bit 2

VID 2 R 0

Bit 1

VID 1 R 0

Bit 0

VID 0 R 1

SMBus Table: Byte Count Register

Pin # Name Control Function Type 0 1 Defaul

t

Bit 7

BC7 RW 0

Bit 6

BC6 RW 0

Bit 5

BC5 RW 0

Bit 4

BC4 RW 0

Bit 3

BC3 RW 1

Bit 2

BC2 RW 0

Bit 1

BC1 RW 1

Bit 0

BC0 RW 0

SMBus Table: Device ID Register

Pin # Name Control Function T

y

pe 0 1 Defaul

t

Bit 7

DID7 R - - 0

Bit 6

DID6

R- - 0

Bit 5

DID5 R - - 0

Bit 4

DID4

R- - 1

Bit 3

DID3 R - - 0

Bit 2

DID2 R - - 1

Bit 1

DID1 R - - 1

Bit 0

DID0 R - - 1

SMBus Table: M/N Programming & Control Register

Pin # Name Control Function T

y

pe 0 1 Defaul

t

Bit 7

M/N_EN

SRC

M/N Programming

Enable

RW Disable Enable 0

Bit 6

0

Bit 5

0

Bit 4

0

Bit 3

0

Bit 2

0

Bit 1

0

Bit 0

0

SMBus Table: SRC/PCI Frequency Control Register

Pin # Name Control Function Type 0 1 Defaul

t

Bit 7

SRC N Div8 N Divider Prog bit 8 RW X

Bit 6

SRC N Div9 N Divider Prog bit 9 RW X

Bit 5

SRC M Div5 RW X

Bit 4

SRC M Div4 RW X

Bit 3

SRC M Div3 RW X

Bit 2

SRC M Div2 RW X

Bit 1

SRC M Div1 RW X

Bit 0

SRC M Div0 RW X

Byte 7

-

REVISION ID 0011 for A rev

-

VENDOR ID 0001 for ICS/IDT

-

Writing to this register will

configure how many bytes will

be read back, default is A

bytes (0 to 9)

-

Byte 8

-

Byte Count

Programming b(7:0)

RESERVED

-

Byte 9

Device ID

(17 hex)

Byte 10

-

-RESERVED

Byte 11

-

The decimal representation of

M and N Divider in Byte 11

and 12 will configure the SRC

VCO frequency. Default at

pow er up = latch-in or Byte 6

Rom table. VCO Frequency =

25 x [ NDiv(9:0)+8] /

[

MDiv

(

5:0

)

+2

]

-

M Divider Programming

bit (5:0)

-

932SQ428

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS

IDT®

PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 15

932SQ428 REV E 042312

SMBus Table: SRC Frequency Control Register

Pin # Name Control Function Type 0 1 Defaul

t

Bit 7

SRC N Div7 RW X

Bit 6

SRC N Div6 RW X

Bit 5

SRC N Div5 RW X

Bit 4

SRC N Div4 RW X

Bit 3

SRC N Div3 RW X

Bit 2

SRC N Div2 RW X

Bit 1

SRC N Div1 RW X

Bit 0

SRC N Div0 RW X

SMBus Table: SRC Spread Spectrum Control Re

g

ister

Pin # Name Control Function Type 0 1 Defaul

t

Bit 7

SRC SSP7 RW X

Bit 6

SRC SSP6 RW X

Bit 5

SRC SSP5 RW X

Bit 4

SRC SSP4 RW X

Bit 3

SRC SSP3 RW X

Bit 2

SRC SSP2 RW X

Bit 1

SRC SSP1 RW X

Bit 0

SRC SSP0 RW X

SMBus Table: SRC Spread Spectrum Control Register

Pin # Name Control Function Type 0 1 Defaul

t

Bit 7

0

Bit 6

SRC SSP14 R

W

X

Bit 5

SRC SSP13 R

W

X

Bit 4

SRC SSP12 R

W

X

Bit 3

SRC SSP11 R

W

X

Bit 2

SRC SSP10 R

W

X

Bit 1

SRC SSP9 R

W

X

Bit 0

SRC SSP8 RW X

SMBus Table: NS_SAS Frequency Control Register

Pin # Name Control Function Type 0 1 Defaul

t

Bit 7

NS_SAS N Div8 N Divider Prog bit 8 RW X

Bit 6

NS_SAS N Div9 N Divider Prog bit 9 RW X

Bit 5

NS_SAS M Div5 RW X

Bit 4

NS_SAS M Div4 RW X

Bit 3

NS_SAS M Div3 RW X

Bit 2

NS_SAS M Div2 RW X

Bit 1

NS_SAS M Div1 RW X

Bit 0

NS_SAS M Div0 RW X

SMBus Table: NS_SAS Frequenc

y

Control Re

g

ister

Pin # Name Control Function Type 0 1 Defaul

t

Bit 7

NS_SAS N Div7 RW X

Bit 6

NS_SAS N Div6 RW X

Bit 5

NS_SAS N Div5 RW X

Bit 4

NS_SAS N Div4 RW X

Bit 3

NS_SAS N Div3 RW X

Bit 2

NS_SAS N Div2 RW X

Bit 1

NS_SAS N Div1 RW X

Bit 0

NS_SAS N Div0 RW X

N Divider Programming

Byte12 bit(7:0) and

Byte11 b it(7:6)

The decimal representation of

M and N Divider in Byte 11

and 12 will configure the SRC

VCO frequency. Default at

power up = latch-in or Byte 6

Rom table. VCO Frequency =

25 x [NDiv(9:0)+8] /

[

MDiv

(

5:0

)

+2

]

-

Byte 12

-

- Reserved

-

Byte 13

-

Spread Spectrum

Programming bit(7:0)

These Spread Spectrum bits in

Byte 13 and 14 will program

the spread pecentage of SRC

-

Byte 14

-

Spread Spectrum

Programming bit(14:8)

These Spread Spectrum bits in

Byte 13 and 14 will program

the spread pecentage of SRC

-

The decimal representation of

M and N Divider in Byte 15

and 16 w ill configure the

NS_SAS VCO frequency.

Default at power up = latch-in

or Byte 0 Rom table. VCO

Frequency = 25 x

[

NDiv

(

9:0

)

+8

]

/

[

MDiv

(

5:0

)

+2

]

-

M Divider Programming

bits (Fixed at 1 for Rev

D)

-

Byte 15

-

Byte 16

-

N Divider Programming

b(7:0)

Th

e

d

ec

i

ma

l

represen

t

a

ti

on o

f

M and N Divider in Byte 15

and 16 w ill configure the

NS_SAS VCO frequency.

Default at power up = latch-in

or Byte 0 Rom table. VCO

Frequency = 25 x

[

NDiv

(

9:0

)

+8

]

/

[

MDiv

(

5:0

)

+2

]

-

932SQ428AKLFT

932SQ428AKLFT

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