932SQ428
PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
IDT®
PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 4
932SQ428 REV E 042312
Pin Descriptions (cont.)
35 AVDDNS PWR 3.3V
p
ower for the non-s
p
readin
g
SAS PLL analo
g
circuits.
36 GNDNS PWR Ground
p
in for non-s
p
readin
g
differential out
p
uts and lo
g
ic.
37 VDD PWR 3.3V
p
ower for core lo
g
ic
38 GND PWR Ground
p
in for core lo
g
ic.
39 SMBDATA I/O Data
p
in of SMBUS circuitr
y
, 5V tolerant
40 SMBCLK IN Clock
p
in of SMBUS circuitr
y
, 5V tolerant
41 GND14 PWR Ground
p
in for 14MHz out
p
ut and lo
g
ic.
42 AVDD14 PWR Analo
g
p
ower
p
in for 14MHz PLL
43 VDD14 PWR Power
p
in for 14MHz out
p
ut and lo
g
ic, nominal 3.3V
44 REF14_3x OUT 14.318 MHz reference clock. 3X drive stren
g
th as default
45 GND14 PWR Ground
p
in for 14MHz out
p
ut and lo
g
ic.
46 GNDXTAL PWR Ground
p
in for Cr
y
stal Oscillator.
47 X1_25 IN Cr
y
stal in
p
ut, Nominall
y
25.00MHz.
48 X2_25 OUT Cr
y
stal out
p
ut, Nominall
y
25.00MHz.
932SQ428
PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
IDT®
PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 5
932SQ428 REV E 042312
Test Loads and Recommended Terminations
Differential Zo
Rp Rp
HSCL Output
Buffer
932SQ420 Differential Test Loads
Rs
Rs
2pF 2pF
Single-ended Output Termination Table
Output Loads
Zo = 50
Zo =6 0
PCI/USB 1 36 43
PCI/USB 2 22 33
REF 1 39 47
REF 2 27 36
REF 3 10 20
Rs Value
(for each load)
932SQ428
Differential Output Termination Table
DIF Zo (
)Iref (
)Rs (
)Rp (
)
100 475 33 50
85 412 27 42.2 or 43.2
932SQ428
PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
IDT®
PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 6
932SQ428 REV E 042312
Electrical Characteristics - Absolute Maximum Ratings
Electrical Characteristics - Current Consumption
DC Electrical Characteristics - Differential Current Mode Outputs
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
3.3V Core Supply Voltage VDDA 4.6 V 1,2
3.3V Logic Supply Voltage VDD 4.6 V 1,2
Input Low Voltage V
IL
GN D-0 .5 V 1
Input High Voltage V
IH
Except for SMBus interface V
DD
+0. 5V V
1
Input High Voltage V
IH SMB
SMBus clock and data pins 5.5V V 1
Storage Temperature Ts -65 150
°
C1
Junction Temperature Tj 125 °C
1
Input ESD protection
ESD prot Human Body Model 2000 V
1
1
Guaranteed by design and characterization, not 100% tested in production.
2
O
p
eration under these conditions is neither im
p
lied nor
g
uaranteed.
TA = T
COM;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Operating Supply Current I
DD3.3OP
All outputs active @100MHz, C
L
= Full load;
250 300 m A 1
Powerdown Current
I
DD3.3PD Z
All differential pairs tri-stated 12 20 mA
1
1
Guaranteed b
y
desi
g
n and characterization, not 100% tested in
p
roduction.
T
A
= T
COM;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Slew rate Trf Sco
p
e avera
g
in
g
on 1 2.4 4
V/ns
1, 2, 3
Slew rate matching
Δ
Trf
Slew rate matching, Scope
avera
g
in
g
on
920
%
1, 2, 4
Rise/Fall Time Variation
Δ
Trf
Rise/fall variation, Scope
avera
g
in
g
off
18 125
ps
1, 7, 8
Volta
g
e Hi
g
hVHi
g
h 660 772 850 1
Volta
g
e Low VLow -150 9 150 1
Max Volta
g
e Vmax 810 1150 1, 7
Min Volta
g
e Vmin -300 -17 1, 7
Vswin
g
Vswin
g
Sco
p
e avera
g
in
g
off 300 1446 mV 1, 2
Crossing Voltage (abs) Vcross_abs Scope averaging off 250 351 550 mV 1, 5
Crossing Voltage (var)
Δ
-Vcross Scope averaging off 24 140 mV 1, 6
2
Measured from differential waveform
7
Includes overshoot and undershoot.
Statistical measurement on
single-ended signal using
mV
Measurement on single ended
signal using absolute value.
mV
1
Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xR
R
). For R
R
= 475
(1%), I
REF
= 2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0 .7V @ Z
O
=50
(100
differential impedance).
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate for Clock and falling edg e rate for Clock#. It is measured using a +/-75mV window centered on the
average cross po int where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage w here Clock = Clock# measured on a component test board and only applies to the differential rising edge
(i.e. Clock rising and Clock# falling).
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross a bsolut e)
allow ed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.

932SQ428AKLFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner CK420BQ
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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