932SQ428
PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS
IDT®
PCIE GEN 2/3 & QPI CLOCK FOR ROMLEY-BASED SERVERS 8
932SQ428 REV E 042312
AC Electrical Characteristics - Differential Current Mode Outputs
Electrical Characteristics - Phase Jitter Parameters
TA = T
COM;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Duty Cycle t
DC
Measured differentially, PLL
Mode
45 50.1 55 % 1
Skew, Output to Output
t
sk3SRC
Across all SRC outputs,
V
T
= 50%
13.5 50 ps 1
SRC, NS_SAS out puts 35 50 ps 1,3
DOT96 output 75 250 ps 1,3
1
Gua ranteed b
desi
n and characterization, not 100 % tested in
roduction.
REF
DD
R
R
REF
OH
REF
OH
O
=50
Ω
.
3
Measured from differential waveform
Jitter, Cycle to cycle
t
jc y c- c yc
T
A
= 0 - 70°C; Supply Voltage V
DD/
V
DDA
= 3.3 V +/-5%,
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
t
hPCIeG1
PCIe Gen 1 28 86 ps (p-p) 1,2,3,6
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.9 3
ps
(rms)
1,2,6
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
(rms)
1,2,6
t
jphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR =
10MHz)
0.4
1
ps
(rms)
1,2,4,6
QPI & SMI
(100MHz or 133MHz, 4.8Gb/s,
6.4Gb/s 12UI)
0.15 0.5
ps
(rms)
1,5,6
QPI & SMI
(100MHz, 8.0Gb/s, 12UI)
(rms)
1,5,6
QPI & SMI
(100MHz, 9.6Gb/s, 12UI)
0.11 0.2
ps
(rms)
1,5,6
t
jphSAS12G
SAS12G
(Filtered REFCLK Jitter 20KHz
to 20MHz.)
0.34 0.4
ps
(rms)
1,7,8
t
jphSAS12G
SAS 12G 0.70 1.3
ps
(rms)
1,5,7
1
Guaranteed by design and characterization, not 100% tested in production.
6
Applies to SRC outputs
7
Applies to NS_SAS, NS_SRC outputs, Spread Off
8
Intel calculation from raw phase noise data
t
jphPCIeG2
4
Subject to final radification by PCI SIG.
5
Calculated from Intel-supplied Clock Jitter Tool v 1.6.6
3
Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
t
jphQPI_SMI
Phase Jitter
2
See http://www.pcisig.com for complete specs