L9951 / L9951XP Functional description of the SPI
Doc ID 14173 Rev 9 23/36
4.4 Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and will go from
high impedance to a low or high level depending on the status bit 0 (fault condition). The first
rising edge of the CLK input after a high to low transition of the CSN pin will transfer the
content of the selected status register into the data out shift register. Each subsequent
falling edge of the CLK will shift the next bit out.
4.5 Serial clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data input
(DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the
falling edge of the CLK signal.
4.6 Input data register
The device has two input registers. The first bit (bit 0) at the DI-input is used to select one of
the two input registers. All bits are first shifted into an input shift register. After the rising
edge of CSN the contents of the input shift register will be written to the selected input data
register only if a frame of exact 16 data bits are detected. Depending on bit 0 the contents of
the selected status register will be transferred to DO during the current communication
frame. Bit 1-8 control the behavior of the corresponding driver. The bits 9,10 and 11 are
used to control the current monitor multiplexer. Bit 15 is used to reset all status bits in both
status registers. The bits in the status registers will be cleared after the current
communication frame (rising edge of CSN).
4.7 Status register
This devices uses two status registers to store and to monitor the state of the device. Bit 0 is
used as a fault bit and is a logical-NOR combination of bits 1-14 in both status registers. The
state of this bit can be polled by the microcontroller without the need of a full SPI-
communication cycle (see Figure 8.). If one of the over-current bits is set, the corresponding
driver will be disabled. If the over-current recovery bit of the output is not set the
microcontroller has to clear the over-current bit to enable the driver. If the thermal shutdown
bit is set, all drivers will go into a high impedance state. Again the microcontroller has to
clear the bit to enable the drivers.
4.8 Test mode
The test mode can be entered by rising the CSN input to a voltage higher than 7.5V. In the
test mode the inputs CLK, DI, PWM and the internal 2MHz CLK can be multiplexed to data
output DO for testing purpose. Furthermore the over-current thresholds are reduced by a
factor of 4 to allow EWS testing at lower current. The internal logic prevents that the Hi-Side
and Low-Side driver of the same half-bridge can be switched-on at the same time. In the test
mode this combination is used to multiplex the desired signals to the CM output according to
table 18 and 19.
