N01S818HA
http://onsemi.com
3
Basic Operation
The 1 Mb serial SRAM is designed to interface directly
with a standard Serial Peripheral Interface (SPI) common on
many standard micro-controllers in the default state. It may
also interface with other non-SPI ports by programming
discrete I/O lines to operate the device.
The serial SRAM contains an 8-bit instruction register and
is accessed via the SI pin. The CS
pin must be low and the
HOLD
pin must be high for the entire operation. Data is
sampled on the first rising edge of SCK after CS
goes low.
If the clock line is shared, the user can assert the HOLD
input
and place the device into a Hold mode. After releasing the
HOLD
pin, the operation will resume from the point where
it was held. The Hold operation is only supported in SPI and
DUAL modes.
By programming the device through a command
instruction, the dual and quad access modes may be initiated.
In these modes, multiplexed I/O lines take the place of the
SPI SI and SO pins and along with the CS
and SCK control
the device in a SPI-like, two bit (DUAL) and four bit
(QUAD) wide serial manner. Once the device is put into
either the DUAL or QUAD mode, the device will remain
operating in that mode until powered down or the Reset
Mode operation is programmed.
The following table contains the possible instructions and
formats. All instructions, addresses and data are transferred
MSB first and LSB last.
Table 4. INSTRUCTION SET
Instruction Command Description
READ 03h Read data from memory starting at selected address
WRITE 02h Write (program) data to memory starting at selected address
EQIO 38h Enable QUAD I/O access
EDIO 3Bh Enable DUAL I/O access
RSTQIO FFh Reset from QUAD and DUAL to SPI I/O access
RDMR 05h Read mode register
WRMR 01h Write mode register
DEVICE OPERATIONS
Read Operation
The serial SRAM Read operation is started by by enabling
CS
low. First, the 8-bit Read instruction is transmitted to the
device through the SI (or SIO0-3) pin(s) followed by the
24-bit address with the 7 MSBs of the address being “don’t
care” bits and ignored. In SPI mode, after the READ
instruction and address bits are sent, the data stored at that
address in memory is shifted out on the SO pin after the
output valid time. Additional “dummy” clock cycles (four in
DUAL and two in QUAD) are required to follow the
instruction and address inputs prior to the data being driven
out on the SIO0-3 pins while operating in these two modes.
By continuing to provide clock cycles to the device, data
can continue to be read out of the memory array in
sequentially. The internal address pointer is automatically
incremented to the next higher address after each byte of
data is read out until the highest memory address is reached.
When the highest memory address is reached, 1FFFFh, the
address pointer wraps to the address 00000h. This allows the
read cycles to be continued indefinitely. All Read operations
are terminated by pulling CS
high.
Figure 2. SPI Read Sequence (Single Byte)
CS
Instruction
SI
043251698107 11
SCK
23 22 21 20 210
7
6543210High−Z
24−bit address
Data Out
SO
29 3130 32 36 37 38 3934 3533
000 00011
