N01S818HA
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5
Write Operation
The serial SRAM WRITE is selected by enabling CS low.
First, the 8-bit WRITE instruction is transmitted to the
device followed by the 24-bit address with the 7 MSBs being
don’t care. After the WRITE instruction and addresses are
sent, the data to be stored in memory is shifted in on the SI
pin.
If operating in page mode, after the initial word of data is
shifted in, additional data words can be written as long as the
address requested is sequential on the same page. Simply
write the data on SI pin and continue to provide clock pulses.
The internal address pointer is automatically incremented to
the next higher address on the page after each word of data
is written in. This can be continued for the entire page length
of 32 words long. At the end of the page, the addresses
pointer will be wrapped to the 0 word address within the
page and the operation can be continuously looped over the
32 words of the same page. The new data will replace data
already stored in the memory locations.
If operating in burst mode, after the initial word of data is
shifted in, additional data words can be written to the next
sequential memory locations by continuing to provide clock
pulses. The internal address pointer is automatically
incremented to the next higher address after each word of
data is read out. This can be continued for the entire array
and when the highest address is reached, 1FFFFh, the
address counter wraps to the address 00000h. This allows
the burst write cycle to be continued indefinitely. Again, the
new data will replace data already stored in the memory
locations.
All WRITE operations are terminated by pulling CS
high.
Figure 6. SPI Write Sequence
CS
Instruction
SI
043251698107 11
SCK
23 22 21 20 21076543210
High−Z
24−bit address Data In to ADDR 1
SO
29 3130 32 36 37 38 3934 3533
000 00 010
7 6543210
Data In to ADDR 2
7 6543210 7 6543210
...
40 4241 43 47 48 49 5045 4644 51 5352 54 55
ADDR 1
Data In to ADDR 3 Data In to ADDR n
High−Z
