©2002 Fairchild Semiconductor Corporation Rev. B January 2002
ISL9N302AP3
PSPICE Electrical Model
SUBCKT ISL9N302AP3 2 1 3 ; rev Nov 2001
CA 12 8 9e-9
Cb 15 14 5.5e-9
Cin 6 8 1e-8
Dbody 7 5 DbodyMOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 30.4
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Evthres 6 21 19 8 1
Evtemp 20 6 18 22 1
It 8 17 1
Lgate 1 9 5.618e-9
Ldrain 2 5 1e-9
Lsource 3 7 1.98e-9
RLgate 1 9 56.1
RLdrain 2 5 15
RLsource 3 7 19.8
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 4e-4
Rgate 9 20 5.93e-1
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 1.3e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),3))}
.MODEL DbodyMOD D (IS=2e-10 N=1.05 RS=1.8e-3 TRS1=9e-4 TRS2=1e-6 + CJO=4.9e-9 M=4.9e-1 TT=1e-13 XTI=0)
.MODEL DbreakMOD D (RS=2.5e-1 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=3.5e-9 IS=1e-30 N=10 M=4.7e-1)
.MODEL MstroMOD NMOS (VTO=2.1 KP=550 IS=1e-25 N=10 TOX=1 L=1u W=1u)
.MODEL MmedMOD NMOS (VTO=1.6 KP=30 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=5.93e-1)
.MODEL MweakMOD NMOS (VTO=1.22 KP=1e-1 IS=1e-40 N=10 TOX=1 L=1u W=1u RG=5.93 RS=1e-1)
.MODEL RbreakMOD RES (TC1=1e-3 TC2=-7e-7)
.MODEL RdrainMOD RES (TC1=1.2e-2 TC2=2.5e-5)
.MODEL RSLCMOD RES (TC1=3.5e-9 TC2=5e-6)
.MODEL RsourceMOD RES (TC1=1e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-2.9e-3 TC2=-9e-6)
.MODEL RvtempMOD RES (TC1=-1.8e-3 TC2=1e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-1.5)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-1.5 VOFF=-3.5)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.4 VOFF=0.1)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.1 VOFF=-0.4)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
18
22
+
-
6
8
+
-
5
51
+
-
19
8
+
-
17
18
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
©2002 Fairchild Semiconductor Corporation Rev. B January 2002
ISL9N302AP3
SABER Electrical Model
REV Nov 2001
template ISL9N302AP3 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl=2e-10,nl=1.05,rs=1.8e-3,trs1=9e-4,trs2=1e-6,cjo=4.9e-9,m=4.9e-1,tt=1e-13,xti=0)
dp..model dbreakmod = (rs=2.5e-1,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=3.5e-9,isl=10e-30,nl=10,m=4.7e-1)
m..model mstrongmod = (type=_n,vto=2.1,kp=550,is=1e-25, tox=1)
m..model mmedmod = (type=_n,vto=1.6,kp=30,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.22,kp=1e-1,is=1e-40, tox=1,rs=1e-1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-3.5,voff=-1.5)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-1.5,voff=-3.5)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.4,voff=0.1)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.1,voff=-0.4)
c.ca n12 n8 = 5e-9
c.cb n15 n14 = 5.5e-9
c.cin n6 n8 = 1e-8
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11 n7 n17 n18 = 30.4
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evthres n6 n21 n19 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
i.it n8 n17 = 1
l.lgate n1 n9 = 5.618e-9
l.ldrain n2 n5 = 1e-9
l.lsource n3 n7 = 1.98e-9
res.rlgate n1 n9 = 56.1
res.rldrain n2 n5 = 15
res.rlsource n3 n7 = 19.8
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1=1e-3,tc2=-7e-7
res.rdrain n50 n16 = 4e-4, tc1=1.2e-2,tc2=2.5e-5
res.rgate n9 n20 = 5.93e-1
res.rslc1 n5 n51 = 1e-6, tc1=3.5e-9,tc2=5e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 1.3e-3, tc1=1e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-2.9e-3,tc2=-9e-6
res.rvtemp n18 n19 = 1, tc1=-1.8e-3,tc2=1e-6
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 3))
}
18
22
+
-
6
8
+
-
19
8
+
-
17
18
6
8
+
-
5
8
+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA
CB
EGS EDS
14
8
13
8
14
13
MWEAK
EBREAK
DBODY
RSOURCE
SOURCE
11
7
3
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES
16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE
RGATE
EVTEMP
9
ESG
LGATE
RLGATE
20
+
-
+
-
+
-
6
©2002 Fairchild Semiconductor Corporation Rev. B January 2002
ISL9N302AP3
SPICE Thermal Model
REV May 2001
TISL9N302AP3
CTHERM1 th 6 4.5e-3
CTHERM2 6 5 2e-2
CTHERM3 5 4 1.5e-2
CTHERM4 4 3 2.5e-2
CTHERM5 3 2 7e-2
CTHERM6 2 tl 2.5e-1
RTHERM1 th 6 2e-3
RTHERM2 6 5 8.5e-3
RTHERM3 5 4 6e-2
RTHERM4 4 3 8e-2
RTHERM5 3 2 9e-2
RTHERM6 2 tl 1e-1
SABER Thermal Model
SABER thermal model TISL9N302AP3
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 4.5e-3
ctherm.ctherm2 6 5 = 2e-2
ctherm.ctherm3 5 4 = 1.5e-2
ctherm.ctherm4 4 3 = 2.5e-2
ctherm.ctherm5 3 2 = 7e-2
ctherm.ctherm6 2 tl = 2.5e-1
rtherm.rtherm1 th 6 =2e-3
rtherm.rtherm2 6 5 = 8.5e-3
rtherm.rtherm3 5 4 = 6e-2
rtherm.rtherm4 4 3 = 8e-2
rtherm.rtherm5 3 2 = 9e-2
rtherm.rtherm6 2 tl = 1e-1
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th
JUNCTION
CASE

ISL9N302AP3

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
MOSFET N-Channel PWM Logic Level
Lifecycle:
New from this manufacturer.
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