SL23EP05
10 Rev. 2.2
8. External Components and Design Considerations
Figure 1. Typical Application Schematic
8.1. Comments and Recommendations
Decoupling Capacitor: A minimum decoupling capacitor of 0.1 F must be used between VDD and VSS on the
pins 6 and 4. Additional capacitors may be necessary depending on the application. Place the capacitor on the
component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and to the GND via
should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD pin.
Series Termination Resistor: A series termination resistor is recommended if the distance between the output
(SSCLK) and the load is over 1.5 inches. The nominal impedance of the SSCLK output is about 30 . Use 20
resistor in series with the output to terminate 50 trace impedance and place 20 resistor as close to the clock
outputs as possible.
Zero Delay and Skew Control: All outputs and CLKIN pins should be loaded with the same load to achieve “Zero
Delay” between the CLKIN and the outputs. The CLKOUT pin is connected to CLKIN internally on-chip for internal
feedback to PLL, and sees an additional 2 pF load with respect to the clock pins. For applications requiring zero
input/output delay, the load at the all output pins including the CLKOUT pin must be the same. If any delay
adjustment is required, the capacitance at the CLKOUT pin could be increased or decreased to increase or
decrease the delay between clocks and CLKIN.
For minimum pin-to-pin skew, the external load at the clocks must be the same.
Not Recommended
for New Designs
