SL23EP05
6 Rev. 2.2
Table 4. AC Electrical Specifications (V
DD
= 3.3 V and 2.5 V)
Parameter Symbol Test Condition Min Typ Max Unit
PLL Lock Time[9] tPLLOCK From 90% of V
DD
to valid clocks presented
on all output clock pins
— — 1.0 ms
Cycle-to-cycle Jitter CCJ
*
3.3 V supply, >66 MHz, <15 pF,
Standard Drive
— 50 125 ps
3.3 V supply, >66 MHz, <30 pF,
High Drive
— 70 140 ps
3.3 V supply, >66 MHz, <30 pF,
Standard Drive
— 80 170 ps
2.5 V supply, >66 MHz, <15 pF,
High Drive
— 50 80 ps
2.5 V supply, >66 MHz, <15 pF,
Standard Drive
— 90 200 ps
2.5 V supply, >66 MHz, <30 pF,
High Drive
— 100 250 ps
Peak Period Jitter
PPJ
*
3.3 V supply, >100 MHz, <15 pF,
Standard Drive
—3065ps
3.3 V supply, 66–100 MHz, <15 pF,
Standard Drive
—4075ps
3.3 V supply, >66 MHz, <30 pF,
High Drive
— 60 120 ps
3.3 V supply, >66 MHz, <30 pF,
Standard Drive
— 70 150 ps
2.5 V supply, > 100 MHz, <15 pF,
High Drive
— 20 45 ps
2.5 V supply, 66–100 MHz, <15 pF,
High Drive
— 20 60 ps
2.5 V supply, >66 MHz, <15 pF,
Standard Drive
— 60 120 ps
*Note: Typical jitter is measured at 3.3 V or 2.5 V, 30ºC with all outputs driven into the maximum specified load.
Not Recommended
for New Designs