SL23EP05
Rev. 2.2 9
2. General Description
The SL23EP05 is a low skew, low jitter Zero Delay Buffer with very low operating current.
The product includes an on-chip high performance PLL that locks into the input reference clock and produces five
output clock drivers tracking the input reference clock for systems requiring clock distribution.
3. Input and Output Frequency Range
The input and output frequency range is the same. However, it depends on V
DD
and drive levels as given in the
below Table 8.
If the input clock frequency is DC (0 to V
DD
), this is detected by an input frequency detection circuitry and all five
clock outputs are forced to Hi-Z. The PLL is shutdown to save power. In this shutdown state, the product draws
less than 10 A supply current.
4. SpreadThru™ Feature
If a Spread Spectrum Clock (SSC) were to be used as an input clock, the SL23EP05 is designed to pass the
modulated Spread Spectrum Clock (SSC) signal from its reference input to the output clocks. The same spread
characteristics at the input are passed through the PLL and drivers without any degradation in spread percent (%),
spread profile and modulation frequency.
5. High and Low-Drive Product Options
The SL23EP05 is offered with High-Drive “–1H” and Standard-Drive “–1” options. These drive options enable the
users to control load levels, frequency range and EMI control. Refer to the AC electrical tables for the details.
6. Skew and Zero Delay
All outputs should drive the similar load to achieve output-to-output skew and input-to-output specifications given in
the AC electrical tables. However, Zero delay between input and outputs can be adjusted by changing the loading
of CLKOUT relative to the banks A and B clocks since CLKOUT is the feedback to the PLL.
7. Power Supply Range (V
DD
)
The SL23EP05 is designed to operate in a wide power supply range from 2.250 V (Min) to 3.360 V (Max). This
power supply range complies with 3.3 V+/–10% and 2.5 V+/–10% standard power supply requirements used in
most systems. An internal on-chip voltage regulator is used to supply PLL constant power supply of 1.8 V, leading
to a consistent and stable PLL electrical performance in terms of skew, and jitter and power dissipation.
Table 8. Input/Output Frequency Range
V
DD
(V) Drive Min (MHz) Max (MHz)
3.3 HIGH 10 220
3.3 STD 10 200
2.5 HIGH 10 180
2.5 STD 10 167
Not Recommended
for New Designs
