10
Figure 23. Typical ATF-54143 LNA with Passive Biasing.
Capacitors C2 and C5 provide a low impedance in-band
RF bypass for the matching networks. Resistors R3 and
R4 provide a very important low frequency termina-
tion for the device. The resistive termination improves
low frequency stability. Capacitors C3 and C6 provide
the low frequency RF bypass for resistors R3 and R4.
Their value should be chosen carefully as C3 and C6
ATF-54143 Applications Information
Introduction
Avago Technologies’ ATF-54143 is a low noise
enhancement mode PHEMT designed for use in low
cost commercial applications in the VHF through 6 GHz
frequency range. As opposed to a typical depletion
mode PHEMT where the gate must be made negative
with respect to the source for proper operation, an
enhancement mode PHEMT requires that the gate
be made more positive than the source for normal
operation. Therefore a negative power supply voltage is
not required for an enhancement mode device. Biasing
an enhancement mode PHEMT is much like biasing the
typical bipolar junction transistor. Instead of a 0.7V base
to emitter voltage, the ATF-54143 enhancement mode
PHEMT requires about a 0.6V potential between the
gate and source for a nominal drain current of 60 mA.
Matching Networks
The techniques for impedance matching an en-
hancement mode device are very similar to those for
matching a depletion mode device. The only di erence
is in the method of supplying gate bias. S and Noise
Parameters for various bias conditions are listed in
this data sheet. The circuit shown in Figure 23 shows a
typical LNA circuit normally used for 900 and 1900 MHz
applications (Consult the Avago Technologies website
for application notes covering speci c applications).
High pass impedance matching networks consisting
of L1/C1 and L4/C4 provide the appropriate match for
noise gure, gain, S11 and S22. The high pass structure
also provides low frequency gain reduction which can
be bene cial from the standpoint of improving out-of-
band rejection at lower frequencies.
also provide a termination for low frequency mixing
products. These mixing products are as a result of two
or more in-band signals mixing and producing third
order in-band distortion products. The low frequency or
di erence mixing products are bypassed by C3 and C6.
For best suppression of third order distortion products
based on the CDMA 1.25 MHz signal spacing, C3 and C6
should be 0.1 μF in value. Smaller values of capacitance
will not suppress the generation of the 1.25 MHz di er-
ence signal and as a result will show up as poorer two
tone IP3 results.
Bias Networks
One of the major advantages of the enhancement mode
technology is that it allows the designer to be able to dc
ground the source leads and then merely apply a positive
voltage on the gate to set the desired amount of quiescent
drain current I
d
.
Whereas a depletion mode PHEMT pulls maximum
drain current when V
gs
= 0V, an enhancement mode
PHEMT pulls only a small amount of leakage current
when V
gs
=0V. Only when V
gs
is increased above V
to
,
the device threshold voltage, will drain current start to
ow. At a V
ds
of 3V and a nominal V
gs
of 0.6V, the drain
current I
d
will be approximately 60 mA. The data sheet
suggests a minimum and maximum V
gs
over which
the desired amount of drain current will be achieved.
It is also important to note that if the gate terminal is
left open circuited, the device will pull some amount of
drain current due to leakage current creating a voltage
di erential between the gate and source terminals.
Passive Biasing
Passive biasing of the ATF-54143 is accomplished by
the use of a voltage divider consisting of R1 and R2. The
voltage for the divider is derived from the drain voltage
which provides a form of voltage feedback through the
use of R3 to help keep drain current constant. Resistor
R5 (approximately 10k) provides current limiting for
the gate of enhancement mode devices such as the
ATF-54143. This is especially important when the device
is driven to P
1dB
or P
SAT
.
Resistor R3 is calculated based on desired V
ds
, I
ds
and
available power supply voltage.
R3 = V
DD
– V
ds
(1)
p
I
ds
+ I
BB
V
DD
is the power supply voltage.
V
ds
is the device drain to source voltage.
I
ds
is the desired drain current.
V
dd
Z
o
L2 L3
C2
C3
L1
J1
R4
R5
C5
C6
L4
R3
R1 R2
C1
Z
o
C4
Q1
OUTPUT
INPUT
J2
