13
Figure 25. Adding Vias to the ATF-54143 Non-Linear Model for Comparison to Measured S and Noise Parameters.
DRAIN
VIA2
V1
D=20.0 mil
H=25.0 mil
T=0.15 mil
Rho=1.0
W=40.0 mil
VIA2
V2
D=20.0 mil
H=25.0 mil
T=0.15 mil
Rho=1.0
W=40.0 mil
VIA2
V4
D=20.0 mil
H=25.0 mil
T=0.15 mil
Rho=1.0
W=40.0 mil
SOURCE
GATESOURCE
ATF-54143
MSUB
MSub1
H=25.0 mil
Er=9.6
Mur=1
Cond=1.0E+50
Hu=3.9e+034 mil
T=0.15 mil
TanD=0
Rough=0 mil
MSub
VIA2
V3
D=20.0 mil
H=25.0 mil
T=0.15 mil
Rho=1.0
W=40.0 mil
For Further Information
The information presented here is an introduction
to the use of the ATF-54143 enhancement mode
PHEMT. More detailed application circuit information
is available from Avago Technologies. Consult the web
page or your local Avago Technologies sales representa-
tive.
Designing with S and Noise Parameters and the Non-Linear
Model
The non-linear model describing the ATF-54143
includes both the die and associated package model.
The package model includes the e ect of the pins but
does not include the e ect of the additional source
inductance associated with grounding the source leads
through the printed circuit board. The device S and
Noise Parameters do include the e ect of 0.020 inch
thickness printed circuit board vias. When comparing
simulation results between the measured S parameters
and the simulated non-linear model, be sure to include
the e ect of the printed circuit board to get an accurate
comparison. This is shown schematically in Figure 25.
14
Noise Parameter Applications Information
F
min
values at 2 GHz and higher are based on measure-
ments while the F
mins
below 2 GHz have been extrapo-
lated. The F
min
values are based on a set of 16 noise
gure measurements made at 16 di erent impedances
using an ATN NP5 test system. From these measure-
ments, a true F
min
is calculated. F
min
represents the true
minimum noise  gure of the device when the device is
presented with an impedance matching network that
transforms the source impedance, typically 50ý, to an
impedance represented by the re ection coe cient G
o
.
The designer must design a matching network that will
present G
o
to the device with minimal associated circuit
losses. The noise  gure of the completed ampli er is
equal to the noise  gure of the device plus the losses
of the matching network preceding the device. The
noise  gure of the device is equal to F
min
only when
the device is presented with G
o
. If the re ection coef-
cient of the matching network is other than G
o
, then
the noise  gure of the device will be greater than F
min
based on the following equation.
NF = F
min
+ 4 R
n
|
s
o
|
2
Zo (|1 +
o
|
2
)(1 - |
s
|
2
)
Where R
n
/Z
o
is the normalized noise resistance, G
o
is
the optimum re ection coe cient required to produce
F
min
and G
s
is the re ection coe cient of the source
impedance actually presented to the device. The losses
of the matching networks are non-zero and they will
also add to the noise  gure of the device creating a
higher ampli er noise  gure. The losses of the matching
networks are related to the Q of the components and
associated printed circuit board loss. G
o
is typically fairly
low at higher frequencies and increases as frequency is
lowered. Larger gate width devices will typically have a
lower G
o
as compared to narrower gate width devices.
Typically for FETs, the higher G
o
usually infers that an
impedance much higher than 50ý is required for the
device to produce F
min
. At VHF frequencies and even
lower L Band frequencies, the required impedance can
be in the vicinity of several thousand ohms. Matching
to such a high impedance requires very hi-Q compo-
nents in order to minimize circuit losses. As an example
at 900 MHz, when airwwound coils (Q>100) are used for
matching networks, the loss can still be up to 0.25 dB
which will add directly to the noise  gure of the device.
Using muiltilayer molded inductors with Qs in the 30
to 50 range results in additional loss over the airwound
coil. Losses as high as 0.5 dB or greater add to the
typical 0.15 dB F
min
of the device creating an ampli er
noise  gure of nearly 0.65 dB. A discussion concerning
calculated and measured circuit losses and their e ect
on ampli er noise  gure is covered in Avago Technolo-
gies Application 1085.
15
Ordering Information
Part Number No. of Devices Container
ATF-54143-TR1G 3000 7” Reel
ATF-54143-TR2G 10000 13”Reel
ATF-54143-BLKG 100 antistatic bag
Package Dimensions
Outline 43 (SO%-343/SC70 4 lead)
HE
D
A2
A1
b
b1
E
1.30 (.051)
BSC
1.15 (.045) BSC
C
L
A
DIMENSIONS (mm)
MIN.
1.15
1.85
1.80
0.80
0.80
0.00
0.15
0.55
0.10
0.10
MAX.
1.35
2.25
2.40
1.10
1.00
0.10
0.40
0.70
0.20
0.46
SYMBOL
E
D
HE
A
A2
A1
b
b1
c
L
NOTES:
1. All dimensions are in mm.
2. Dimensions are inclusive of plating.
3. Dimensions are exclusive of mold ash & metal burr.
4. All specications comply to EIAJ SC70.
5. Die is facing up for mold and facing down for trim/form,
ie: reverse trim/form.
6. Package surface to be mirror nish.
Recommended PCB Pad Layout for
Avago’s SC70 4L/SOT-343 Products
1.30
(0.051)
0.60
(0.024)
0.9
(0.035)
Dimensions in
mm
(inches)
1.15
(0.045)
2.00
(0.079)
1.00
(0.039)

ATF-54143-BLKG

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
RF JFET Transistors Transistor GaAs Single Voltage
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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