13
FN6749.1
December 15, 2011
register resets both the WEL and RWEL bits. A read
operation occurring between any of the previous operations
will not interrupt the register write operation.
Alarm Operation
Since the alarm works as a comparison between the alarm
registers and the RTC registers, it is ideal for notifying a host
processor of a particular time event and trigger some action
as a result. The host can be notified by either a hardware
interrupt (the IRQ
/F
OUT
pin) or by polling the Status Register
(SR) Alarm bits. These two volatile bits (AL1 for Alarm 1 and
AL0 for Alarm 0), indicate if an alarm has happened. The bits
are set on an alarm condition regardless of whether the
IRQ
/F
OUT
interrupt is enabled. The AL1 and AL0 bits in the
status register are reset by the falling edge of the eighth
clock of status register read.
There are two alarm operation modes: Single Event and
periodic Interrupt Mode:
1. Single Event Mode is enabled by setting the AL0E or
AL1E bit to “1”, the IM bit to “0”, and disabling the
frequency output. This mode permits a one-time match
between the alarm registers and the RTC registers. Once
this match occurs, the AL0 or AL1 bit is set to “1” and the
IRQ/
F
OUT
output will be pulled low and will remain low
until the AL0 or AL1 bit is read, which will automatically
resets it. Both Alarm registers can be set at the same time
to trigger alarms. The IRQ/
F
OUT
output will be set by
either alarm, and will need to be cleared to enable
triggering by a subsequent alarm. Polling the SR will
reveal which alarm has been set.
2. Interrupt Mode (or “Pulsed Interrupt Mode” or PIM) is
enabled by setting the AL0E or AL1E bit to “1” the IM bit
to “1”, and disabling the frequency output. If both AL0E
and AL1E bits are set to 1, then only the AL0E PIM alarm
will function (AL0E overrides AL1E). The IRQ/
F
OUT
output will now be pulsed each time an alarm occurs. This
means that once the Interrupt Mode alarm is set, it will
continue to alarm for each occurring match of the alarm
and present time. This mode is convenient for hourly or
daily hardware interrupts in microcontroller applications
such as security cameras or utility meter reading.
Interrupt Mode CANNOT be used for general periodic
alarms, however, since a specific time period cannot be
programmed for interrupt, only matches to a specific time
of day. The Interrupt Mode is only stopped by disabling
the IM bit or the Alarm Enable bits.
Writing to the Alarm Registers
The Alarm Registers are non-volatile but require special
attention to insure a proper non-volatile write takes place.
Specifically, byte writes to individual registers are good for all
but registers 0006h and 0000Eh, which are the DWA0 and
DWA1 registers, respectively. Those registers will require a
special page write for nonvolatile storage. The
recommended page write sequences are as follows:
1. 16-byte page writes: The best way to write or update the
Alarm Registers is to perform a 16-byte write beginning at
address 0001h (MNA0) and wrapping around and ending
at address 0000h (SCA0). This will insure that
non-volatile storage takes place. This means that the
code must be designed so that the Alarm0 data is written
starting with Minutes register, and then all the Alarm1
data, with the last byte being the Alarm0 Seconds (the
page ends at the Alarm1 Y2k register and then wraps
around to address 0000h).
Alternatively, the 16-byte page write could start with
address 0009h, wrap around and finish with address
0008h. Note that any page write ending at address 0007h
or 000Fh (the highest byte in each Alarm) will not trigger a
non-volatile write, so wrapping around or overlapping to
the following Alarm's Seconds register is advised.
2. Other non-volatile writes: It is possible to do writes of
less than an entire page, but the final byte must always
be addresses 0000h through 0004h or 0008h though
000Ch to trigger a non-volatile write. Writing to those
blocks of 5 bytes sequentially, or individually, will trigger a
non-volatile write. If the DWA0 or DWA1 registers need to
be set, then enough bytes will need to be written to
overlap with the other Alarm register and trigger the
non-volatile write. For Example, if the DWA0 register is
being set, then the code can start with a multiple byte
write beginning at address 0006h, and then write 3 bytes
ending with the SCA1 register as follows:
Addr Name
0006h DWA0
0007h Y2K0
0008h SCA1
If the Alarm1 is used, SCA1 would need to have the correct
data written.
Power Control Operation
The power control circuit accepts a V
DD
and a V
BAT
input.
Many types of batteries can be used with Intersil RTC
products. For example, 3.0V or 3.6V Lithium batteries are
appropriate, and battery sizes are available that can power
an Intersil RTC device for up to 10 years. Another option is
to use a Super Cap for applications where V
DD
is interrupted
for up to a month. See the “Application Section” on page 20
for more information.
There are two options for setting the change-over conditions
from V
DD
to Battery Backup Mode. The BSW bit in the PWR
register controls this operation:
• Option 1 - Standard Mode
• Option 2 - Legacy Mode (Default)
Note that the I
2
C bus may or may not be operational during
battery backup, which is controlled by the SBIB bit. See
“Backup Battery Operation” on page 21 for information.
The V
DD
/V
BAT
power circuit also contains a glitch detection
circuit to protect from incorrect serial bus writes after a
brownout situation. This circuit disables the serial bus for
about 90ms following the power-up. To trigger the delay, the
ISL12024IRTC
