22
FN6749.1
December 15, 2011
to 10 years. Another option is to use a super capacitor for
applications where V
DD
may disappear intermittently for short
periods of time. Depending on the value of superconductor
used, backup time can last from a few days to two weeks (with
>1F). A simple silicon or Schottky barrier diode can be used in
series with V
DD
to charge the superconductor, which is
connected to the V
BAT
pin. Try to use Schottky diodes with
very low leakages, <1µA desirable. Do not use the diode to
charge a battery (especially lithium batteries!)
There are two possible modes for battery backup operation;
Standard and Legacy Mode. In Standard Mode, there are no
operational concerns when switching over to battery backup
since all other devices functions are disabled. Battery drain
is minimal in Standard Mode, and return to Normal V
DD
powered operations is predictable. In Legacy Mode, the
V
BAT
pin can power the chip if the voltage is above V
DD
and
less than V
TRIP
. In this mode, it is possible to generate alarm
and communicate with the device, unless SBI = 1, but the
supply current drain is much higher than the Standard Mode
and backup time is reduced. In this case if alarms are used
in backup mode, the IRQ
/F
OUT
pull-up resistor must be
connected to V
BAT
voltage source. During initial power-up
the default mode is the Standard Mode.
Alarm Operation Examples
Below are examples of both Single Event and periodic
Interrupt Mode alarms.
EXAMPLE 1
Alarm0 set with single interrupt (IM = “0”)
A single alarm will occur on January 1 at 11:30am.
A. Set Alarm0 registers as follows:
B. Also, the AL0E bit must be set as follows:
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30am on January 1 (after
seconds changes from 59 to 00) by setting the AL0 bit in the
status register to “1” and also bringing the IRQ/
F
OUT
output
low.
EXAMPLE 2
Pulsed interrupt once per minute (IM = “1”)
Interrupts at one minute intervals when the seconds register
is at 30 seconds.
A. Set Alarm0 registers as follows:
B. Set the Interrupt register as follows:
Once the registers are set, the following waveform will be
seen at IRQ/
F
OUT
:
ALARM0
REGISTER
BIT
DESCRIPTION76543210HEX
SCA0 00000000 00hSeconds disabled
MNA0 10110000 B0hMinutes set to 30,
enabled
HRA0 10010001 91hHours set to 11,
enabled
DTA0 10000001 81hDate set to 1,
enabled
MOA0 10000001 81hMonth set to 1,
enabled
FIGURE 24. SUPER CAPACITOR CHARGING CIRCUIT
V
DD
V
BAT
V
SS
SUPER CAPACITO
2.7V TO 5.5V
DWA0 00000000 00hDay of week
disabled
CONTROL
REGISTER
BIT
DESCRIPTION76543210HEX
INT 00100000 x0hEnable Alarm
ALARM0
REGISTER
BIT
DESCRIPTION76543210HEX
SCA0 10110000B0hSeconds set to 30,
enabled
MNA0 0000000000hMinutes disabled
HRA0 0000000000hHours disabled
DTA0 0000000000hDate disabled
MOA0 0000000000hMonth disabled
DWA0 0000000000hDay of week disabled
CONTROL
REGISTER
BIT
DESCRIPTION76543210HEX
INT 10100000x0hEnable Alarm and Int
Mode
ALARM0
REGISTER
BIT
DESCRIPTION76543210HEX
60s
RTC AND ALARM REGISTERS ARE BOTH 30s
FIGURE 25.
ISL12024IRTC
