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ISL12024IRTCZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
4
FN6749.1
December 15, 2011
EEPROM Specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
EEPROM Endurance 2,000,000 Cycles
EEPROM Retention Temperature ≤ +75°C 50 Years
Serial Interface (I
2
C) Specifications
DC Electrical Specifications
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 12) TYP
MAX
(Note 12) UNITS NOTES
V
IL
SDA, and SCL Input Buffer LOW
Voltage
-0.3 0.3 x V
DD
V
V
IH
SDA, and SCL Input Buffer HIGH
Voltage
0.7 x V
DD
V
DD
+ 0.3 V
Hysteresis SDA and SCL Input Buffer Hysteresis 0.05 x V
DD
V9, 11
V
OL
SDA Output Buffer LOW Voltage I
OL
= 4mA 0 0.4 V
I
LI
Input Leakage Current on SCL V
IN
= 5.5V 100 nA
I
LO
I/O Leakage Current on SDA V
IN
= 5.5V 100 nA
AC Electrical Specifications
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 12) TYP
MAX
(Note 12) UNITS NOTES
f
SCL
SCL Frequency 400 kHz
t
IN
Pulse width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed.
50 ns
t
AA
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30% of V
DD
, until
SDA exits the 30% to 70% of V
DD
window.
900 ns
t
BUF
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of V
DD
during a STOP
condition, to SDA crossing 70% of V
DD
during
the following START condition.
1300 ns
t
LOW
Clock LOW Time Measured at the 30% of V
DD
crossing. 1300 ns
t
HIGH
Clock HIGH Time Measured at the 70% of V
DD
crossing. 600 ns
t
SU:STA
START Condition Set-up Time SCL rising edge to SDA falling edge. Both
crossing 70% of V
DD
.
600 ns
t
HD:STA
START Condition Hold Time From SDA falling edge crossing 30% of V
DD
to
SCL falling edge crossing 70% of V
DD
.
600 ns
t
SU:DAT
Input Data Set-up Time From SDA exiting the 30% to 70% of V
DD
window, to SCL rising edge crossing 30% of
V
DD
.
100 ns
t
HD:DAT
Input Data Hold Time From SCL rising edge crossing 70% of V
DD
to
SDA entering the 30% to 70% of V
DD
window.
0ns
t
SU:STO
STOP Condition Set-up Time From SCL rising edge crossing 70% of V
DD
, to
SDA rising edge crossing 30% of V
DD
.
600 ns
t
HD:STO
STOP Condition Hold Time for
Read, or Volatile Only Write
From SDA rising edge to SCL falling edge. Both
crossing 70% of V
DD
.
600 ns
t
DH
Output Data Hold Time From SCL falling edge crossing 30% of V
DD
,
until SDA enters the 30% to 70% of V
DD
window.
0ns
ISL12024IRTC
5
FN6749.1
December 15, 2011
Timing Diagrams
Bus Timing
Write Cycle Timing
Cpin SDA and SCL Pin Capacitance 10 pF 9, 11
t
WC
Non-Volatile Write Cycle Time 12 20 ms 10
t
R
SDA and SCL Rise Time From 30% to 70% of V
DD
20+0.1xCb 300 ns 9, 11
t
F
SDA and SCL Fall Time From 70% to 30% of V
DD
20+0.1xCb 300 ns 9, 11
Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip. 10 400 pF 9, 11
R
PU
SDA and SCL Bus Pull-up Resistor
Off-chip
Maximum is determined by t
R
and t
F
.
For Cb = 400pF, max is about 2kΩ~2.5kΩ.
For Cb = 40pF, max is about 15kΩ~20kΩ
1kΩ 9, 11
NOTES:
3. IRQ/
F
OUT
Inactive.
4. V
IL
= V
DD
x 0.1, V
IH
= V
DD
x 0.9, f
SCL
= 400kHz
5. V
DD
> V
BAT
+V
BATHYS
6. Bit BSW = 0 (Standard Mode), ATR = 00h, V
BAT
≥1.8V
7. Specified at +25°C.
8. In order to ensure proper timekeeping, the V
DD SR-
specification must be followed.
9. Limits established by characterization and are not production tested.
10. t
WC
is the minimum cycle time to be allowed for any non-volatile Write by the user (it is the time from valid STOP condition at the end of Write
sequence of a serial interface Write operation) to the end of the self-timed internal non-volatile write cycle.
11. These are I
2
C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
AC Electrical Specifications (Continued)
SYMBOL PARAMETER TEST CONDITIONS
MIN
(Note 12) TYP
MAX
(Note 12) UNITS NOTES
t
SU:STO
t
DH
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
t
F
t
LOW
t
BUF
t
AA
t
R
t
HD:STO
SCL
SDA
t
WC
8TH BIT OF LAST BYTE ACK
STOP
CONDITION
START
CONDITION
ISL12024IRTC
6
FN6749.1
December 15, 2011
Typical Performance Curves Temperature is +25°C unless otherwise specified.
FIGURE 1. I
BAT
vs V
BAT,
SBIB = 0 FIGURE 2. I
BAT
vs V
BAT,
SBIB = 1
FIGURE 3. I
DD3
vs TEMPERATURE FIGURE 4. I
BAT
vs TEMPERATURE
FIGURE 5. I
DD3
vs V
DD
FIGURE 6. ΔF
OUT
vs ATR SETTING
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3
V
BAT
(V)
I
BAT
(µA)
SCL, SDA PULL-UPS = 0V
SCL, SDA PULL-UPS = V
BAT
BSW = 0 OR 1
BSW = 0 OR 1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3
V
BAT
(V)
I
BAT
(µA)
SCL, SDA PULL-UPS = 0V
BSW = 0 OR 1
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-45-35-25-15-5 5 1525354555657585
TEMPERATURE (°C)
I
DD
(µA)
V
DD
= 3.3V
V
DD
= 5.5V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
-45-35-25-15-5 5 1525354555657585
TEMPERATURE (°C)
IBAT (µA)
V
BAT
= 3.0V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
1.82.32.83.33.84.34.85.3
V
DD
(V)
I
DD
(µA)
-40
-20
0
20
40
60
80
-32 -28 -24 -20 -16 -12 -8 -4 0 4 8 12 16 20 24 28
ATR SETTING
PPM CHANGE FROM ATR = 0
ISL12024IRTC
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

ISL12024IRTCZ

Mfr. #:
Buy ISL12024IRTCZ
Manufacturer:
Renesas / Intersil
Description:
Real Time Clock RTC OUTPUT PROGRAM TO 32KHZ W/EEPROM 8
Lifecycle:
New from this manufacturer.
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