ISL80101IRAJZ

1
DATASHEET
High Performance 1A LDO
ISL80101-ADJ
The ISL80101-ADJ is a low voltage, high current, single output
LDO specified at 1A output current. This LDO operates from
input voltages from 2.2V to 6V, and is capable of providing
output voltages from 0.8V to 5V. The ISL80101-ADJ features
an adjustable output. For the fixed output version of the
ISL80101-ADJ, please refer to the ISL80101
datasheet.
A submicron BiCMOS process is utilized for this product family
to deliver the best in class analog performance and overall
value. This CMOS LDO will consume significantly lower
quiescent current as a function of load compared to bipolar
LDOs, which translates into higher efficiency and packages
with smaller footprints. State of the art internal compensation
achieves a very fast load transient response. An external
capacitor on the soft-start pin provides an adjustable
soft-starting ramp. The ENABLE feature allows the part to be
placed into a low quiescent current shutdown mode. A
Power-good logic output signals a fault condition.
Table 1
shows the differences between the ISL80101-ADJ and
others in its family:
Features
•±1.8% V
OUT
accuracy guaranteed over line, load and
T
J
= -40°C to +125°C
Very low 130mV dropout voltage at V
OUT
= 2.5V
Very fast transient response
•Programmable soft-starting
Power-good output
Excellent 65dB PSRR
Current limit protection
•Thermal shutdown function
Available in a 10 Ld DFN package
Pb-Free (RoHS compliant)
Applications
DSP, FPGA and µP core power supplies
Noise-sensitive instrumentation systems
Post regulation of switched mode power supplies
Industrial systems
Medical equipment
Telecommunications and networking equipment
•Servers
Hard disk drives (HD/HDD)
Related Literature
AN1592, “ISL80101 High Performance 1A LDO Evaluation
Board User Guide”
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART NUMBER
PROGRAMMABLE
I
LIMIT
I
LIMIT
(DEFAULT)
ADJ OR FIXED
V
OUT
ISL80101-ADJ No 1.75A ADJ
ISL80101 No 1.75A 1.8V, 2.5V,
3.3V, 5.0V
ISL80101A Yes 1.62A ADJ
ISL80121-5 Yes 0.75A 5.0V
FIGURE 1. TYPICAL APPLICATION CIRCUIT
FIGURE 2. DROPOUT vs LOAD CURRENT
V
IN
PGENABLE
SS
GND
V
IN
1
2
5
4
7
10
9
6
10k
100k
10µF
2.5V ± 10%
1.8V
ADJ
2.61k
1.00k
ISL80101-ADJ
C
SS
C
PB
C
OUT
R
3
0.01µF
R
2
R
1
82pF
3
10µF
C
IN
V
OUT
V
OUT
R
PG
0
20
40
60
80
100
120
140
0 0.2 0.4 0.6 0.8 1.0
OUTPUT CURRENT (A)
DROPOUT VOLTAGE (mV)
V
OUT
= 2.5V
August 26, 2015
FN7834.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL80101-ADJ
2
FN7834.3
August 26, 2015
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Block Diagram
REFERENCE
+
SOFT-START
CONTROL
LOGIC
THERMAL
SENSOR
FET DRIVER
WITH CURRENT
LIMIT
-
+
EA
V
IN
EN
GND
V
OUT
+
-
PG
PG
ADJ
SS
Ordering Information
PART NUMBER
(Notes 3
, 4)
PART
MARKING
V
OUT
VOLTAGE
(Note 2
)
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant) PKG DWG. #
ISL80101IRAJZ (Note 1
) DZAB ADJ -40 to +125 10 Ld 3x3 DFN L10.3x3
ISL80101EVAL2Z Evaluation Board
NOTES:
1. Add “-T*” for Tape and Reel. Please refer to TB347
for details on reel specifications.
2. For other output voltages, contact Intersil Marketing.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see product information page for ISL80101-ADJ
. For more information on MSL please see techbrief
TB363
.
ISL80101-ADJ
3
FN7834.3
August 26, 2015
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Pin Configurations
ISL80101-ADJ
(10 LD 3x3 DFN)
TOP VIEW
2
3
4
1
5
9
8
7
10
6
V
OUT
V
OUT
ADJ
PG
GND
V
IN
V
IN
NC
ENABLE
SS
EPAD
Pin Descriptions
PIN NUMBER PIN NAME DESCRIPTION
1, 2 V
OUT
Regulated output voltage. A X5R/X7R output capacitor is required for stability. See External Capacitor
Requirements” on page 8 for more details.
3 ADJ This pin is connected to the feedback resistor divider and provides voltage feedback signals for the LDO to set the
output voltage. In addition, the PGOOD circuit uses this input to monitor the output voltage status.
4 PG This is an open-drain logic output used to indicate the status of the output voltage. Logic low indicates V
OUT
is not
in regulation. Must be grounded if not used.
5GNDGround
6 SS External capacitor on this pin adjusts start-up ramp and controls inrush current.
7ENABLE V
IN
independent chip enable. TTL and CMOS compatible.
8 NC No connection; Leave floating.
9, 10 V
IN
Input supply; A minimum of 10µF X5R/X7R input capacitor is required for proper operation. See External
Capacitor Requirements” on page 8 for more details.
- EPAD EPAD at ground potential. It is recommended to solder the EPAD to the ground plane.

ISL80101IRAJZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
LDO Voltage Regulators SINGLE 1A ADJ VOUTLD 3X3 10LD W/ANN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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