ISL80101-ADJ
10
FN7834.3
August 26, 2015
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE REVISION CHANGE
August 26, 2015 FN7834.3 Added Related Literature to page 1.
Removed 1st bullet in Features on page 1 which read ±0.2% initial VOUT accuracy.
Changed 7th bullet in Features on page 1 from Excellent 58dB PSRR at 1kHz to Excellent 65dB PSRR
Updated the EA amp in the “Block Diagram” on page 2 by switching the + and - terminals. The positive
terminal is now connected to the ADJ pin. Removed “SENSE” pin Reference in diagram
“Pin Descriptions” on page 3 - Removed “minimum 10µF” from 1st sentence in V
OUT
description.
“Absolute Maximum Ratings” on page 4 - Removed Machine Model and changed latch up from +85°C to
+125°C.
Removed "SENSE" from “ADJ” in "‘Recommended Operating Conditions" on page 4.
Added “V
IN
=” to values in Figure 10 on page 7
Changed Title of Figure 3 on page 6 from Dropout vs Temperature to Dropout Voltage vs Temperature
Changed Title in Figure 12 on page 7 from PSRR vs Frequency and Load Current to PSRR vs Frequency for
various load currents
Changed Title in Figure 13 on page 7 from PSRR vs Frequency and Output Capacitance (I
OUT
= 100mA) to
PSRR vs Frequency for various output capacitors (I
OUT
=100mA)
Electrical Spec changes:
Electrical Spec Table conditions on page 4 changed: V
IN
= V
OUT
+ 0.4V, V
OUT
= 1.8V, C
IN
= C
OUT
= 2.2µF, to:
2.2V < V
IN
< 6V, V
OUT
= 0.5V
“Feedback Pin (ADJ Option Only)” Test Conditions changed from: 2.2V V
IN
6V, 0A < I
LOAD
< 1A to: V
OUT
+
0.4V < V
IN
< 6V, V
OUT
= 2.5V, 0A < I
LOAD
< 1A
"DC Input Line Regulation" on page 4 - changed symbol from V
OUT
/V
IN
to V
OUT
low line - V
OUT
high
line)/V
OUT
low line and added MIN -1. Test Conditions changed from: V
OUT
+ 0.5V < V
IN
< 5V to: V
OUT
+ 0.4V
< V
IN
< 6V, V
OUT
= 2.5V
“DC Output Load Regulation” on page 4 - changed symbol from V
OUT
/I
OUT
to
V
OUT
no load-V
OUT
high load)/
V
OUT
no load and added MAX 1. Test Conditions changed from: 0A < I
LOAD
< 1A, All voltage options to: 0A <
I
LOAD
< 1A, V
OUT
= 2.5V
Ground Pin Current Test Conditions changed from:
I
LOAD
= 0A, 2.2V < V
IN
< 6V to: I
LOAD
= 0A, V
OUT
+ 0.4V < V
IN
< 6V, V
OUT
= 2.5V
I
LOAD
= 1A, 2.2V < V
IN
< 6V to: I
LOAD
= 1A, V
OUT
+ 0.4V < V
IN
< 6V, V
OUT
= 2.5V
Output Short Circuit Current Test Conditions changed from: V
OUT
= 0V, 2.2V < V
IN
< 6V to: V
OUT
= 0V
Thermal Shutdown Temperature, Thermal Shutdown Hysteresis, Turn-on Threshold and Hysteresis - Removed
Test Conditions
Removed “Rising Threshold” from ““Thermal Shutdown Hysteresis” on page 4 and from “Hysteresis” on page 5
“AC CHARACTERISTICS” on page 4 in PSRR - changed TYP from "72" to "65" for f = 120Hz. Added to Test
Conditions: V
OUT
= 1.8V
Output Noise Voltage in test conditions changed “10Hz” to “100Hz”, added V
IN
= 2.2V, V
OUT
= 1.8V. Changed
TYP from “63” to “53”
“PG Flag Low Voltage” on page 5 changed in test conditions - V
IN
= 2.5V TO V
IN
= 3V
“Turn-on Threshold” on page 5 changed MIN from: 0.3; to: 0.5
“Hysteresis” on page 5 changed in test conditions from: 2.2V < V
OUT
+ 0.4V < 6V, to: 2.2V < V
IN
< 6V
“ENABLE Pin Leakage Current” on page 5 changed “Enable = 3V” to “Enable = 2.8V”
-------------------------------------------------
Updated Output Spectral Noise Density (Figure 15 on page 8) and changed I
L
= 1A to I
OUT
= 1A
Updated POD L10.3x3 to most recent revision with changes as follows:
Added missing dimension 0.415 in Typical Recommended land pattern.
Shortened the e-pad rectangle on both the recommended land pattern and the package bottom view to line
up with the centers of the corner pins.
Tiebar Note 4 updated
From: Tiebar shown (if present) is a non-functional feature.
To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends).
