ISL80101-ADJ
9
FN7834.3
August 26, 2015
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and temperature. X7R and X5R dielectric ceramic capacitors are
strongly recommended as they typically maintain a capacitance
range within ±20% of nominal voltage over full operating ratings
of temperature and voltage. This output capacitor must be
connected to the V
OUT
and GND pins of the LDO with PCB traces
no longer than 0.5cm.
Additional capacitors of any value in ceramic, POSCAP,
alum/tantalum electrolytic types may be placed in parallel to
improve PSRR at higher frequencies and/or load transient AC
output voltage tolerances. The use of C
PB
(see following section)
is recommended when only the minimum recommended
ceramic capacitor is used on the output. Please refer to Table 2
for these minimum conditions for various output voltages.
Phase Boost Capacitor
A small phase boost capacitor, C
PB
, can be placed across the top
resistor, R
2
, in the feedback resistor divider network in order to
place a zero at:
This zero increases the crossover frequency of the LDO and
provides additional phase resulting in faster load transient
response.
It is important to note that LDO stability and load transient
performance are affected by the type of output capacitor used.
For optimal result, empirical tuning of C
PB
is suggested for each
specific application. It is recommended to not use C
PB
when high
ESR capacitors such as Aluminum Electrolytic or Tantalum are
used on the output.
Table 2 shows the recommended minimum ceramic C
OUT
and
corresponding C
PB
, R
2
and R
1
for different output voltages.
INPUT CAPACITOR
For proper operation, a minimum capacitance of 10µF X5R/X7R
is required at the input. This ceramic input capacitor must be
connected to the V
IN
and GND pins of the LDO with PCB traces no
longer than 0.5cm.
Power Dissipation and Thermals
The junction temperature must not exceed the range specified in
the “Recommended Operating Conditions” on page 4. The power
dissipation can be calculated by using Equation 5
:
The maximum allowable junction temperature, T
J(MAX)
and the
maximum expected ambient temperature, T
A(MAX)
determine the
maximum allowable power dissipation, as shown in Equation 6:
JA
is the junction-to-ambient thermal resistance.
For safe operation, ensure that the power dissipation P
D
,
calculated from Equation 5
, is less than the maximum allowable
power dissipation P
D(MAX)
.
The DFN package uses the copper area on the PCB as a heatsink.
The EPAD of this package must be soldered to the copper plane
(GND plane) for effective heat dissipation. Figure 16 shows a curve
for the
JA
of
the DFN package for different copper area sizes.
Thermal Fault Protection
The power level and the thermal impedance of the package
(+45°C/W for DFN) determine when the junction temperature
exceeds the thermal shutdown temperature. In the event that the
die temperature exceeds around +160°C, the output of the LDO will
shut down until the die temperature cools down to about +130°C.
Current Limit Protection
The ISL80101-ADJ LDO incorporates protection against overcurrent
due to any short or overload condition applied to the output pin. The
LDO performs as a constant current source when the output current
exceeds the current limit threshold noted in the “Electrical
Specifications” table on page 4
. If the short or overload condition is
removed from V
OUT
, then the output returns to normal voltage
regulation mode. In the event of an overload condition, the LDO may
begin to cycle on and off due to the die temperature exceeding
thermal fault condition and subsequently cooling down after the
power device is turned off.
TABLE 2. RECOMMENDED C
PB
FOR DIFFERENT V
OUT
AND C
OUT
V
OUT
(V)
R
2
(kΩ)
R
1
(kΩ)
C
OUT
(
µF)
C
PB
(pF)
5.0 2.61 0.287 10 100
3.3 2.61 0.464 10 100
2.5 2.61 0.649 10 82
1.8 2.61 1.0 10 82
1.5 2.61 1.3 10 68
1.5 2.61 1.3 22 150
1.2 2.61 1.87 22 120
1.2 2.61 1.87 47 270
1.0 2.61 2.61 47 220
0.8 2.61 4.32 47 220
F
z
1
2xR
2
xC
PB
----------------------------------
=
(EQ. 4)
P
D
V
IN
V
OUT
–I
OUT
V
IN
I
GND
+=
(EQ. 5)
P
DMAX
T
JMAX
T
A
–
JA
=
(EQ. 6)
FIGURE 16. 3mmx3mm 10-PIN DFN ON 4-LAYER PCB WITH
THERMAL VIAS
JA
vs EPAD-MOUNT COPPER LAND
AREA ON PCB
37
39
41
43
45
47
49
24681012141618202224
EPAD-MOUNT COPPER LAND AREA ON PCB, mm
2
JA
°C/W
