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NCP5230MNTWG

P1-P3P4-P6P7-P9P10-P12
NCP5230
http://onsemi.com
4
THERMAL INFORMATION
Rating Symbol Typ Unit
Thermal Resistance, Junction−to−Ambient
R
q
JA
60 °C/W
Thermal Resistance, Junction−to−Case
R
q
JC
18 °C/W
Operating Junction Temperature Range T
J
0 to 125 °C
Operating Ambient Temperature Range T
A
0 to 85 °C
Maximum Storage Temperature Range T
STG
−55 to +150 °C
Moisture Sensitivity Level QFN Package MSL 1 −
ELECTRICAL CHARACTERISTICS Unless otherwise stated: 0°C < T
A
< 85°C; 4.5 V < VCC < 13.2 V; C
VCC
= 0.1 mF
Parameter Test Conditions Min Typ Max Unit
SUPPLY OPERATING CONDITIONS
VCC Voltage Range 4.5 13.2 V
VCCP Voltage Range 4.5 13.2 V
dV/dt on VCC (Note 1) −10 10
V/ms
dV/dt on VCCP (Note 1) −10 10
V/ms
VCC AND BOOT INPUT SUPPLY CURRENT
VCC Operating Current V
CC
= 5 V, EN = High
V
CC
= 12 V, EN = High
5.0 mA
VCC Supply Current V
CC
= 5 V, EN = Low
V
CC
= 12 V, EN = Low
400 uA
VCCP INPUT SUPPLY CURRENT
VCCP Operating Current
UG and LG Open
V
CCP
= 5 V, EN = High
V
CCP
= 12 V, EN = High 3.5 5.0
mA
VCCP Supply Current V
CCP
= 5 V, EN = Low
V
CCP
= 12 V, EN = Low
200
mA
VCC SUPPLY VOLTAGE
VCC UVLO Start Threshold V
CC
Rising 4.50 V
VCC UVLO Hysteresis V
CC
Rising or Falling 300 mV
VCCP SUPPLY VOLTAGE
VCCP UVLO Start Threshold 4.2 V
VCCP UVLO Hysteresis 200 mV
ERROR AMPLIFIER COMP
Open Loop DC Gain (Note 1) 120 dB
Open Loop Unity Gain Bandwidth (Note 1) 15 18 MHz
Slew Rate (Note 1) COMP pin to GND with 100 pF load 8.0
V/ms
VREF
Internal Reference Voltage 0.800 V
Output Voltage Accuracy V
out
to FBG excluding external resistor divider
tolerance
−0.5 0.5 %
CURRENT SENSE AMPLIFIERS
Common Mode Input Voltage Range
(Note 1, GNG, output within 10mV)
V
CC
≤ 7.5 V −0.3 3.5 V
Common Mode Input Voltage Range
(Note 1, GNG, output within 10 mV)
V
CC
> 7.5 V −0.3 5.5 V
1. Guaranteed by design.
2. For propagation delays, ”tpdh” refers to the specified signal going high ”tpdl” refers to it going low. Reference Gate Timing Diagram.
NCP5230
http://onsemi.com
5
ELECTRICAL CHARACTERISTICS Unless otherwise stated: 0°C < T
A
< 85°C; 4.5 V < VCC < 13.2 V; C
VCC
= 0.1 mF
Parameter UnitMaxTypMinTest Conditions
OSCILLATOR (with no ROSC Resistor Defaults to 200 kHz)
Switching Frequency Accuracy R
OSC
open −10 10 %
OSC Gain (Note 1) 10 kHz /
mA
Disable threshold R
OSC
/EN pin, V
dis_th
0.75 V
MODULATORS (PWM Comparators)
Minimum Pulse Width F
sw
= 200 kHz, OSC open 90 ns
Minimum Turn Off Time (LG on) F
sw
= 200 kHz, OSC open 250 350 450 ns
Magnitude of the PWM Ramp V
IN
= 5 V or 12 V 1.50 V
Maximum Duty Cycle OSC/EN = OPEN 80 95 %
Minimum Skip mode frequency In light load, maximum time for LG to turn on
after HG turns off
30 kHz
SOFT−START
Soft Start Time @ 200 kHz 1024 clock cycles, OSC/EN open 5.12 ms
SOFT−OFF
Soft OFF bleeding resistor R
dis
120
W
OVER CURRENT PROTECTION
First Over Current Threshold CSP−CSN, 4xMasking 17 20 23 mV
Second Over Current Threshold CSP−CSN, Immediate action 30 mV
SYNC PIN
Synchronization Input VIL, square wave 1.0 V
Synchronization Input VIH, square wave 2.5 V
PROTECTION AND PGOOD
Output Voltage Logic Low, Sinking 4 mA 0.4 V
OVP Threshold VSEN rising above 1.25 * V
ref
117 125 130 %
UVP Threshold VSEN falling below 0.75 * V
ref
70 75 80 %
Unlatched Overvoltage Threshold V
th_disoff
with respect to 0.5 V
ref
40 50 60 %
Power Good High Delay (Note 1) 50
ms
Power Good Low Delay (Note 1) 1
ms
ZERO CURRENT DETECTION (LX Pin)
Blanking Time before Zero Current
Detection (Note 1)
Blanking Time after LG is < 1.0 V
40 ns
Capture Time for LX Voltage (Note 1) Time to capture LX voltage once LG is < 1.0 V
(must be within dead time limits)
20 ns
Negative LX detection voltage V
bdls
150 300 450 mV
Positive LX detection voltage V
bdhs
0.2 0.5 1.0 V
Time for V
th
adjustment and settling time
(Note 1)
300 kHz 3.0 3.7
ms
Initial Negative Current Detection
Threshold Voltage Set Point (Note 1)
LX−GND, Includes ± 2 mV Offset Range 1.0 mV
V
th
adjustable Range (Note 1) −16 0 15 mV
1. Guaranteed by design.
2. For propagation delays, ”tpdh” refers to the specified signal going high ”tpdl” refers to it going low. Reference Gate Timing Diagram.
NCP5230
http://onsemi.com
6
ELECTRICAL CHARACTERISTICS Unless otherwise stated: 0°C < T
A
< 85°C; 4.5 V < VCC < 13.2 V; C
VCC
= 0.1 mF
Parameter UnitMaxTypMinTest Conditions
HIGH SIDE DRIVER UG
R
H_TG
Output Resistance, Sourcing V
BOOT
− V
LX
= 12 V, C
load
= 3 nF 2.5 5
W
R
H_TG
Output Resistance, Sinking V
BOOT
− V
LX
= 12V 2.0 2.5
W
Tr
DRVH
Transition Time C
LOAD
= 2 nF 16 ns
Tf
DRVH
Transition Time C
LOAD
= 2 nF 11
Tpdh
DRVH
Propagation Delay (Notes 1, 2) Driving High, C
LOAD
= 3 nF,
V
CC
= 12 V, V
CCP
=12 V
15 30 ns
UG Internal Resistor to LX Unbiased, BOOT − LX = 0 45
kW
LOW SIDE DRIVER LG
R
H_BG
Output Resistance, Sourcing V
LX
= GND, C
load
= 3 nF 2.0 3.0
W
R
L_BG
Output Resistance, Sinking V
LX
= V
CC
1.0 1.5
W
Tr
DRVL
Transition Time C
LOAD
= 3 nF 16 ns
Tf
DRVL
Transition Time C
LOAD
= 3 nF 11
Tpdh
DRVL
Propagation Delay (Notes 1, 2) Driving High, C
LOAD
= 3 nF, V
CCP
= 12 V, V
CCP
= 12 V
10 20 35 ns
LX Internal Resistor to GND 45
kW
THERMAL SHUTDOWN
T
sd
Thermal Shutdown (Note 1) 150 180 °C
T
sdhys
Thermal Shutdown Hysteresis
(Note 1)
50 °C
1. Guaranteed by design.
2. For propagation delays, ”tpdh” refers to the specified signal going high ”tpdl” refers to it going low. Reference Gate Timing Diagram.
P1-P3P4-P6P7-P9P10-P12

NCP5230MNTWG

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Manufacturer:
ON Semiconductor
Description:
Switching Controllers BUCK CONTROLLER
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