NCP5230
http://onsemi.com
7
Figure 3. Gate Timing Diagram
1V
1V
Switching Frequency
Connecting a resistor from ROSC/EN to an external
voltage source V
pu
will configure the switching frequency.
Normal range would be 100 kHz to 1 MHz. With no resistor
connected to the pin, the oscillator frequency is 200 kHz.
The switching frequency will follow the relationship:
F
SW
+ 200 kHz *
V
pu
* 1.240
R
OSC
@ 10
kHz
mA
(eq. 1)
When R
osc
= infinity (no resistor connected), F
sw
=
200 kHz; when V
pu
= ground, the frequency programmed
will be higher than 200 kHz. Pulling R
osc
/EN pin to ground
solidly with a less than 10 kW resistor will result in the part
being disabled.
Soft−Start
Soft−Start will begin if VCC, VCCP are both above their
UVLO thresholds and EN pin is set free. IC initially waits
a fixed delay time and then ramps the reference in 5.12 ms
(1024 clock cycles when R
osc
open) in closed−loop
regulation. After soft−start, PGOOD signal will be released
with 3 clock cycles delay.
Protection active during soft−start:
• Overvoltage Protection always enabled;
• Undervoltage Protection is enabled after reference
voltage ramps up to 80% of the final value. During
soft−start, a UVP fault will initiate a complete soft
restart.
Synchronization Function
Synchronize through the SYNC pin. Synchronization
function allows different converters to share the same input
filter reducing the resulting RMS current and reducing the
need for total caps to sustain the load. Synchronized systems
also exhibit higher EMI noise immunity and better
regulation.
The device synchronizes to the Falling edge of the SYNC
pin external input signal (eg. high side gate signal, switch
node signal, distribution clock signal), and locks the phase
of an internal ramp signal correspondingly with a fixed
delay time. The external signal has to sit within a 0-40%
frequency window above the local frequency configured by
the R
osc
resistor to allow the synchronization function
working properly.
Power Good
The PGOOD pin is an open drain connection with no
internal pullup resistor. An active high output signals the
normal operation of the converter. PGOOD is pulled low
during soft-start cycle, and if there is an overvoltage or
undervoltage fault. If the voltage on the VSEN pin is within
±10% of Vref (0.8 V) then the PGOOD pin will not be pulled
low.
Overvoltage Protection (OV)
If the voltage on the VSEN pin exceeds the overvoltage
threshold (1000 mV or 125% Vref), the NCP5230 will latch
an overvoltage fault. During an overvoltage fault event the
UG pin will be pulled low, and the LG pin will stay high until
the voltage on the VSEN pin goes below 400 mV or 50%
V
ref
, then a soft-bleeding resistor will be connected from
switch node to ground to continuously discharge the output
voltage softly. To clear the overvoltage fault, toggling VCC
or EN is needed.
Undervoltage Protection (UV)
If the voltage on the FB pin falls below the undervoltage
threshold after the softstart cycle completes, the NCP5230
will latch an undervoltage fault. During an undervoltage
fault, both the UG and LG pins will be pulled low. Toggling
VCC power or EN will reset the undervoltage protection.
PreOVP Protection
If the NCP5230 is powered on but not enabled, the VSEN
pin will be monitored for preOVP condition. If the VSEN
exceeds the preset threshold, the device will force LG pin
high to protect the load. The PreOVP function will be
disabled when the device is enabled and the normal OV
function will operate instead.
