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AD7884BPZ-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
a
AD7884/AD7885
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
REV. E
LC
2
MOS
16-Bit, High Speed Sampling ADCs
ⴞ3V
IN
F
AD7884
TIMER
CONTROL
DGND
CS
RD
BUSY
DB15
AGNDS
AGNDF
AV
DD
GND
DB0
CONVST
V
DD
9
9
9
16
16
V
REF–
R3
3k⍀
C1
SW1
SW2
9-BIT
ADC
LATCH
+
ALU
O
U
T
P
U
T
D
R
I
V
E
R
S
16-BIT
ACCURATE
DAC
R2
3k⍀
ⴞ3V
IN
S
R1
5k⍀
R5
4k⍀
A2
SW3
R6
2k⍀
R7
2k⍀
R8
2k⍀
ⴞ5V
IN
F
ⴞ5V
IN
S
AV
SS
V
SS
V
REF+
FV
REF+
SV
INV
V
REF–
R4
4k⍀
A1
AD7885
TIMER
CONTROL
DGND
CS
RD
BUSY
DB7
AGNDS
AGNDF
AV
DD
GND
DB0
CONVST
V
DD
9
9
9
16
8
V
REF–
R3
3k⍀
C1
SW1
SW2
9-BIT
ADC
LATCH
+
ALU
O
U
T
P
U
T
D
R
I
V
E
R
S
16-BIT
ACCURATE
DAC
R2
3k⍀
ⴞ3V
IN
R1
5k⍀
R5
4k⍀
A2
SW3
R6
2k⍀
R7
2k⍀
R8
2k⍀
ⴞ5V
IN
F
ⴞ5V
IN
S
AV
SS
V
SS
V
REF+
FV
REF+
SV
INV
V
REF–
R4
4k⍀
HBEN
A1
FEATURES
Monolithic Construction
Fast Conversion: 5.3 ␮ s
High Throughput Rate: 166 kSPS
Low Power: 250 mW
APPLICATIONS
Automatic Test Equipment
Medical Instrumentation
Industrial Control
Data Acquisition Systems
Robotics
GENERAL DESCRIPTION
The AD7884/AD7885 is a 16-bit monolithic analog-to-digital
converter with internal sample-and-hold and a conversion time
of 5.3 µs. The maximum throughput rate is 166 kSPS. It uses a
two-pass flash architecture to achieve this speed. Two input
ranges are available: ±5 V and ± 3 V. Conversion is initiated by
the CONVST signal. The result can be read into a microprocessor
using the CS and RD inputs on the device. The AD7884 has a
16-bit parallel reading structure while the AD7885 has a byte reading
structure. The conversion result is in twos complement code.
The AD7884/AD7885 has its own internal oscillator that controls
conversion. It runs from ±5 V supplies and needs a V
REF+
of 3 V.
The AD7884 is available in a 40-lead CERDIP package and a
44-lead PLCC package.
The AD7885 is available in a 28-lead CERDIP package and the
AD7885A is available in a 44-lead PLCC package.
FUNCTIONAL BLOCK DIAGRAMS
REV. E
–2–
AD7884/AD7885/AD7885A–SPECIFICATIONS
(V
DD
= +5 V ⴞ 5%, V
SS
= –5 V ⴞ 5%,
V
REF+
S = 3 V, AGND = DGND = GND = 0 V, f
SAMPLE
= 166 kHz. All specifications T
MIN
to T
MAX
, unless otherwise noted.)
JAB
Parameter Version
1, 2, 3
Version
1, 2, 3
Version
1, 2, 3
Unit Test Conditions/Comments
DC ACCURACY
Resolution 16 16 16 Bits
Minimum Resolution for Which
No Missing Codes Are Guaranteed 16 16 16 Bits
Integral Nonlinearity ± 0.0075 % FSR max Typically 0.003% FSR
Positive Gain Error ± 0.1 ± 0.03 ± 0.03 % FSR typ AD7885AQ/BQ: 0.1% typ
Positive Gain Error ± 0.05 % FSR max AD7885BQ: 0.2% max
Gain TC
4
± 2 ± 2 ± 2 ppm FSR/°C typ
Bipolar Zero Error ± 0.05 ± 0.05 ± 0.05 % FSR typ
± 0.15 % FSR max
Bipolar Zero TC
4
± 8 ± 8 ± 8 ppm FSR/°C typ
Negative Gain Error ± 0.1 ± 0.03 ± 0.03 % FSR typ AD7885AQ/BQ: 0.1% typ
Negative Gain Error ± 0.05 % FSR max AD7885BQ: 0.2% max
Offset TC
4
± 2 ± 2 ± 2 ppm FSR/°C typ
Noise 120 120 120 µV rms typ 78 µV rms Typical in ± 3 V Input Range
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion) Ratio 82 84 84 dB min Input Signal: ±5 V, 1 kHz Sine Wave, Typically 86 dB
82 82 82 dB typ Input Signal: ± 5 V, 12 kHz Sine Wave
Total Harmonic Distortion –84 –88 –88 dB max Input Signal: ±5 V, 1 kHz Sine Wave
–84 –84 –84 dB typ Input Signal: ± 5 V, 12 kHz Sine Wave
Peak Harmonic or Spurious Noise –88 –88 –88 dB max Input Signal: ± 5 V, 1 kHz Sine Wave
Intermodulation Distortion (IMD)
Second Order Terms –84 –84 –84 dB typ f
A
= 11.5 kHz, f
B
= 12 kHz, f
SAMPLE
= 166 kHz
Third Order Terms –84 –84 –84 dB typ f
A
= 11.5 kHz, f
B
= 12 kHz, f
SAMPLE
= 166 kHz
CONVERSION TIME
Conversion Time 5.3 5.3 5.3 µs max
Acquisition Time 2.5 2.5 2.5 µs max
Throughput Rate 166 166 166 kSPS max There is an overlap between conversion and acquisition.
ANALOG INPUT
Voltage Range ± 5 ± 5 ± 5V
± 3 ± 3 ± 3V
Input Current ± 4 ± 4 ± 4 mA max
REFERENCE INPUT
Reference Input Current ± 5 ± 5 ± 5 mA max V
REF+
S = 3 V
LOGIC INPUTS
Input High Voltage, V
INH
2.4 2.4 2.4 V min V
DD
= 5 V ± 5%
Input Low Voltage, V
INL
0.8 0.8 0.8 V max V
DD
= 5 V ± 5%
Input Current, I
IN
± 10 ± 10 ± 10 µA max Input Level = 0 V to V
DD
Input Capacitance, C
IN
4
10 10 10 pF max
LOGIC OUTPUTS
Output High Voltage, V
OH
4.0 4.0 4.0 V min I
SOURCE
= 200 µA
Output Low Voltage, V
OL
0.4 0.4 0.4 V max I
SINK
= 1.6 mA
DB15–DB0
Floating-State Leakage Current 10 10 10 µA max
Floating-State Output Capacitance
4
15 15 15 pF max
POWER REQUIREMENTS
V
DD
555 V nom ± 5% for Specified Performance
V
SS
–5 –5 –5 V nom ± 5% for Specified Performance
I
DD
35 35 35 mA max Typically 25 mA
I
SS
30 30 30 mA max Typically 25 mA; AD7885/AD7885A
33 33 33 mA max Typically 25 mA; AD7884
Power Supply Rejection Ratio
∆Gain/∆V
DD
86 86 86 dB typ
∆Gain/∆V
SS
86 86 86 dB typ
Power Dissipation 325 325 325 mW max Typically 250
mW
NOTES
1
Temperature ranges are as follows: J, A, B Versions: –40°C to +85°C.
2
V
IN
= ± 5 V.
3
The AD7885AAP has the same specifications as the AD7884AP. The AD7885ABP has the same specifications as the AD7884BP.
4
Sample tested to ensure compliance.
Specifications subject to change without notice.
REV. D
–3–
AD7884/AD7885
TIMING CHARACTERISTICS
1
Limit at 25ⴗC Limit at T
MIN
, T
MAX
Parameter (All Versions) (A, B, and J Versions) Unit Conditions/Comments
t
1
50 50 ns min CONVST Pulsewidth
t
2
100 100 ns max CONVST to BUSY Low Delay
t
3
00 ns min CS to RD Setup Time
t
4
60 60 ns min RD Pulsewidth
t
5
00 ns min CS to RD Hold Time
t
6
2
57 57 ns max Data Access Time after RD
t
7
3
55 ns min Bus Relinquish Time after RD
50 50 ns max
t
8
40 40 ns min New Data Valid before Rising Edge of BUSY
t
9
10 80 ns min HBEN to RD Setup Time
t
10
25 25 ns min HBEN to RD Hold Time
t
11
60 60 ns min HBEN Low Pulse Duration
t
12
60 60 ns min HBEN High Pulse Duration
t
13
55 70 ns max Propagation Delay from HBEN Falling to Data Valid
t
14
55 70 ns max Propagation Delay from HBEN Rising to Data Valid
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
t
6
is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3
t
7
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t
7
, quoted in the Timing Characteristics
is the true bus relinquish time of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
(V
DD
= +5 V ⴞ 5%, V
SS
= –5 V ⴞ 5%, AGND = DGND = GND = 0 V. See Figures 2, 3, 4, and 5.)
TO OUTPUT PIN
2.1V
C
L
100pF
200␮A
I
OH
1.6mA
I
OL
Figure 1. Load Circuit for Access Time and Bus
Relinquish Time
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

AD7884BPZ-REEL

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Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16-Bit Monolithic
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