AD7884BPZ-REEL Datasheet AD7884AQ, AD7884APZ, AD7884APZ-REEL | P10-P12

REV. E

AD7884/AD7885

–10–

USING THE AD7884/AD7885 ANALOG INPUT RANGES

The AD7884/AD7885 can be set up to have either a ±3 V analog

input range or a ±5 V analog input range. Figures 10 and 11 show

the necessary corrections for each of these. The output code is

twos complement and the ideal code table for both input ranges

is shown in Table I.

Reference Considerations

The AD7884/AD7885 operates from a ±3 V reference. This can

be derived simply using the AD780 as shown in Figure 6.

INV

Figure 10.

5 V Input Range Connection

INV

Figure 11.

3 V Input Range Connections

The critical performance specification for a reference in a 16-bit

application is noise. The reference peak-to-peak noise should be

insignificant in comparison to the ADC noise. The AD7884/AD7885

has a typical rms noise of 120 µV. For example, a reasonable

target would be to keep the total rms noise less than 125 µV.

To do this the reference noise needs to be less than 35 µV rms.

In the 100 kHz band, the AD780 noise is less than 30 µV rms,

making it a very suitable reference.

The buffer amplifier used to drive the device V

REF+

should have

low enough noise performance so as not to affect the overall

system noise requirement. The AD845 and AD817 achieve this.

Decoupling and Grounding

The AD7884 and AD7885A have one AV

pin and two V

pins. They also have one AV

pin and three V

pins. The

AD7885 has one AV

pin, one V

pin, one AV

pin, and

one V

pin. Figure 6 shows how a common +5 V supply should

be used for the positive supply pins and a common –5 V supply

for the negative supply pins.

For decoupling purposes, the critical pins on both devices are

the AV

and AV

pins. Each of these should be decoupled to

system AGND with 10 µF tantalum and 0.1 µF ceramic capaci-

tors right at the pins. With the V

and V

pins, it is sufficient

to decouple each of these with ceramic 1 µF capacitors.

AGNDS, AGNDF are the ground return points for the on-chip

9-bit ADC. They should be driven by a buffer amplifier as shown

in Figure 6. If they are tied directly together and then to ground,

there will be a marginal degradation in linearity performance.

The GND pin is the analog ground return for the on-chip lin-

ear circuitry. It should be connected to system analog ground.

The DGND pin is the ground return for the on-chip digital

circuitry. It should be connected to the ground terminal of the

and V

supplies. If a common analog supply is used for

and V

, then DGND should be connected to the com-

mon ground point.

Power Supply Sequencing

and V

are connected to a common substrate and there is

typically 17 Ω resistance between them. If they are powered by

separate 5 V supplies, then these should come up simultaneously.

Otherwise, the one that comes up first will have to drive 5 V

into a 17 Ω load for a short period of time. However, the standard

short-circuit protection on regulators like the 7800 series will

ensure that there is no possibility of damage to the driving device.

should always come up either before or at the same

time as V

. If this cannot be guaranteed, Schottky diodes

should be used to ensure that V

never exceeds AV

more than 0.3 V. Arranging the power supplies as in Figure 6

and using the recommended decoupling ensures that there

are no power supply sequencing issues as well as giving the

specified noise performance.

+5V +5V –5V –5V

AD7884/AD7885

HP5082-2810

EQUIVALENT

Figure 12. Schottky Diodes Used to Protect Against

Incorrect Power Supply Sequencing

Analog Input

ⴞ3 V ⴞ5 V Digital Output

In Terms of FSR

Range

Code Transition

+FSR/2 – 1 LSB 2.999908 4.999847 011 . . . 111 to 111 . . . 110

+FSR/2 – 2 LSBs 2.999817 4.999695 011 . . . 110 to 011 . . . 101

+FSR/2 – 3 LSBs 2.999726 4.999543 011 . . . 101 to 011 . . . 100

AGND + 1 LSB 0.000092 0.000153 000 . . . 001 to 000 . . . 000

AGND 0.000000 0.000000 000 . . . 000 to 111 . . . 111

AGND – 1 LSB –0.000092 –0.000153 111 . . . 111 to 111 . . . 110

–(FSR/2 – 3 LSBs) –2.999726 –4.999543 100 . . . 011 to 100 . . . 010

–(FSR/2 – 2 LSBs) –2.999817 –4.999695 100 . . . 010 to 100 . . . 001

–(FSR/2 – 1 LSB) –2.999908 –4.999847 100 . . . 001 to 100 . . . 000

NOTES

This table applies for V

REF+

S = 3 V.

FSR (full-scale range) is 6 V for the ± 3 V input range and 10 V for the

± 5 V input range.

1 LSB on the ± 3 V range is FSR/2

and is equal to 91.5 µV.

1 LSB on the ± 5 V range is FSR/2

and is equal to 152.6 µV.

Table I. Ideal Output Code Table for the AD7884/AD7885

REV. E

AD7884/AD7885

–11–

AD7884/AD7885 PERFORMANCE

Linearity

The linearity of the AD7884/AD7885 is determined by the

on-chip 16-bit D/A converter. This is a segmented DAC that is

laser trimmed for 16-bit DNL performance to ensure that there

are no missing codes in the ADC transfer function. Figure 13

shows a typical INL plot for the AD7884/AD7885.

16384 32768 49152

65535

OUTPUT CODE

0.5

1.0

1.5

2.0

LINEARITY ERROR – LSBs

= +5V

= –5V

= 25ⴗC

Figure 13. AD7884/AD7885 Typical Linearity Performance

Noise

In an A/D converter, noise exhibits itself as code uncertainty in

dc applications and as the noise floor (in an FFT, for example)

in ac applications.

In a sampling A/D converter like the AD7884/AD7885, all

information about the analog input appears in the baseband

from dc to 1/2 the sampling frequency. An antialiasing filter will

remove unwanted signals above f

/2 in the input signal, but the

converter wideband noise will alias into the baseband. In the

AD7884/AD7885, this noise is made up of sample-and-hold noise

and A/D converter noise. The sample-and-hold section contrib-

utes 51 µV rms and the ADC section contributes 59 µV rms.

These add up to a total rms noise of 78 µV. This is the input

referred noise in the ±3 V analog input range. When operating

in the ± 5 V input range, the input gain is reduced to –0.6. This

means that the input referred noise is now increased by a factor

of 1.66 to 120 µV rms.

Figure 14 shows a histogram plot for 5000 conversions of a dc

input using the AD7884/AD7885 in the ± 5 V input range. The

analog input was set as close as possible to the center of a code

transition. All codes other than the center code are due to the

ADC noise. In this case, the spread is six codes.

3000

2000

1000

CODE FREQUENCY

(X – 2) (X – 1) (X) (X + 1) (X + 2) (X + 3)

CODE

Figure 14. Histogram of 5000 Conversions of a DC Input

If the noise in the converter is too high for an application, it can

be reduced by oversampling and digital filtering. This involves

sampling the input at a higher than the required word rate

and then averaging to arrive at the final result. The very fast

conversion time of the AD7884/AD7885 makes it very

suitable for oversampling. For example, if the required input

bandwidth is 40 kHz, the AD7884/AD7885 could be

oversampled by a factor of 2. This yields a 3 dB

improvement in the effective SNR performance.

The noise

performance in the ±5 V input range is now effectively 85 µV rms,

and the resultant spread of codes for 2500 conversions will be four.

This is shown in Figure 15.

1500

1000

500

CODE FREQUENCY

(X – 1) (X) (X + 1) (X + 2)

CODE

Figure 15. Histogram of 2500 Conversions of a DC Input

Using a

2 Oversampling Ratio

REV. E

AD7884/AD7885

–12–

Dynamic Performance

With a combined conversion and acquisition time of 6 µs, the

AD7884/AD7885 is ideal for wide bandwidth signal processing appli-

cations. Signal-to-(noise + distortion), total harmonic distortion,

peak harmonic or spurious noise, and intermodulation distortion

are all specified. Figure 16 shows a typical FFT plot of a 1.8 kHz,

±5 V input after being digitized by the AD7884/AD7885.

–150

–60

–120

–90

–30

2048 POINT FFT

= 1.8kHz, ⴞ5V SINE WAVE

SAMPLE

= 163kHz

SNR = 87dB

THD = –95dB

Figure 16. AD7884/AD7885 FFT Plot

Effective Number of Bits

The formula for SNR (see Terminology section) is related to

the resolution or number of bits in the converter. Rewriting the

formula, below, gives a measure of performance expressed in

effective number of bits (N).

N SNR=−

()

176 602..

FREQUENCY – kHz

EFFECTIVE NUMBER OF BITS

Figure 17. Effective Number of Bits vs. Frequency

The effective number of bits for a device can be calculated from

its measured SNR. Figure 17 shows a typical plot of effective

number of bits versus frequency for the AD7884. The sampling

frequency is 166 kHz.

MICROPROCESSOR INTERFACING

The AD7884/AD7885 is designed on a high speed process

that results in very fast interfacing timing (data access time of

57 ns max). The AD7884 has a full 16-bit parallel bus, and the

AD7885 has an 8-bit wide bus. The AD7884, with its parallel

interface, is suited to 16-bit parallel machines whereas the

AD7885, with its byte interface, is suited to 8-bit machines.

Some examples of typical interface configurations follow.

AD7884 to MC68000 Interface

Figure 18 shows a general interface diagram for the MC68000

16-bit microprocessor to the AD7884. In Figure 18, conversion

is initiated by bringing CSA low (i.e., writing to the appropriate

address). This allows the processor to maintain control over the

complete conversion process. In some cases, it may be more

desirable to control conversion independent from the processor.

This can be done by using an external sampling timer.

MC68000

AD7884

ADDRESS

DECODE LOGIC

CONVST

DB15–DB0

R/W

DATA BUS

ADDRESS BUS

A23–A1

D15–D0

DTACK

CSA

CSB

Figure 18. AD7884 to MC68000 Interface

Once conversion has been started, the processor must wait until

it is completed before reading the result. There are two ways of

ensuring this. The first way is to simply use a software delay to

wait for 6.5 µs before bringing CS and RD low to read the data.

The second way is to use the BUSY output of the AD7884 to

generate an interrupt in the MC68000. Because of the nature of

its interrupts, the MC68000 requires additional logic (not shown

in Figure 18) to allow it to be interrupted correctly. For full

information on this, consult the MC68000 User’s Manual.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

AD7884BPZ-REEL

Mfr. #:

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Analog to Digital Converters - ADC 16-Bit Monolithic

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