REV. E
AD7884/AD7885
–7–
PIN FUNCTION DESCRIPTIONS
AD7884 AD7885 AD7885A Description
V
INV
V
INV
V
INV
This pin is connected to the inverting terminal of an op amp, as in Figure 6, and allows
the inversion of the supplied 3 V reference.
V
REF–
V
REF–
V
REF–
This is the negative reference input and can be obtained by using an external amplifier to
invert the positive reference input. In this case, the amplifier output is connected to V
REF–
.
See Figure 6.
± 3V
IN
S ± 3V
IN
SThis is the analog input sense pin for the ± 3 V analog input range on the AD7884 and
AD7885A.
± 3V
IN
F ± 3V
IN
FThis is the analog input force pin for the ± 3 V analog input range on the AD7884 and
AD7885A. When using this input range, the ± 5V
IN
F and ± 5V
IN
S pins should be tied to
AGND.
± 3V
IN
This is the analog input pin for the ± 3 V analog input range on the AD7885. When using
this input range, the ±5V
IN
F and ± 5V
IN
S pins should be tied to AGND.
± 5V
IN
S ± 5V
IN
S ± 5V
IN
S This is the analog input sense pin for the ±5 V analog input range on the AD7884, AD7885,
and AD7885A.
± 5V
IN
F ± 5V
IN
F ± 5V
IN
F This is the analog input force pin for the ±5 V analog input range on the AD7884, AD7885,
and AD7885A. When using this input range, the ± 3V
IN
F and ± 3V
IN
S pins should be tied
to AGND.
AGNDS AGNDS AGNDS This is the ground return sense pin for the 9-bit ADC and the on-chip residue amplifier.
AGNDF AGNDF AGNDF This is the ground return force pin for the 9-bit ADC and the on-chip residue amplifier.
AV
DD
AV
DD
AV
DD
Positive analog power rail for the sample-and-hold amplifier and the residue amplifier.
AV
SS
AV
SS
AV
SS
Negative analog power rail for the sample-and-hold amplifier and the residue amplifier.
GND GND GND This is the ground return for the sample-and-hold section.
V
SS
V
SS
V
SS
Negative Supply for the 9-Bit ADC
V
DD
V
DD
V
DD
Positive Supply for the 9-Bit ADC and All Device Logic
CONVST CONVST CONVST This asynchronous control input starts conversion.
CS CS CS Chip Select Control Input
RD RD RD Read Control Input. This is used in conjunction with CS to read the conversion result
from the device output latch.
HBEN HBEN High Byte Enable. Active high control input for the AD7885. It selects either the high or
the low byte of the conversion for reading.
BUSY BUSY BUSY Busy Output. The BUSY output goes low when the conversion begins and stays low until
it is completed, at which time it goes high.
DB0–DB15 16-Bit Parallel Data-Word Output on the AD7884
DB0–DB7 DB0–DB7 8-Bit Parallel Data Byte Output on the AD7885
DGND DGND DGND Ground Return for All Device Logic
V
REF+
FV
REF+
FV
REF+
FReference Force Input
V
REF+
SV
REF+
SV
REF+
SReference Sense Input. The device operates from a 3 V reference.
REV. E
AD7884/AD7885
–8–
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Bipolar Zero Error
This is the deviation of the midscale transition (all 0s to all 1s)
from the ideal (AGND).
Positive Gain Error
This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal (+V
REF+
S – 1 LSB) after bipolar zero
error has been adjusted out.
Negative Gain Error
This is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal (–V
REF+
S + 1 LSB) after bipolar zero
error has been adjusted out.
Signal-to-(Noise + Distortion) Ratio
This is the measured ratio of signal-to-(noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (f
S
/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan-
tization noise. The theoretical signal-to-(noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by
Signal to Noise Distortion N dB−− +
()
=+
()
602 176..
Thus for an ideal 16-bit converter, this is 98 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7884/AD7885, it is
defined as
THD dB
VVVVV
V
() log=
++++
20
2
2
3
2
4
2
5
2
6
2
1
where V
1
is the rms amplitude of the fundamental and V
2
, V
3
,
V
4
, V
5
, and V
6
are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the rms
value of the next largest component in the ADC output spectrum
(up to f
S
/2 and excluding dc) to the rms value of the fundamental.
Normally, the value of this specification is determined by the larg-
est harmonic in the spectrum, but for parts where the harmonics
are buried in the noise floor, it will be a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, and so on. Intermodulation terms are those for
which neither m nor n are equal to zero. For example, the second
order terms include (fa + fb) and (fa – fb), while the third order
terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa – 2fb).
The AD7884/AD7885 is tested using the CCIFF standard where
two input frequencies near the top end of the input bandwidth are
used. In this case, the second and third order terms are of different
significance. The second order terms are usually distanced in
frequency from the original sine waves while the third order terms
are usually at a frequency close to the input frequencies. As a
result, the second and third order terms are specified separately.
The calculation of the intermodulation distortion is as per the THD
specification, where it is the ratio of the rms sum of the individual
distortion products to the rms amplitude of the fundamental
expressed in dB.
Power Supply Rejection Ratio
This is the ratio of the change in positive gain error to the change
in V
DD
or V
SS
, in dB. It is a dc measurement.
OPERATIONAL DIAGRAM
An operational diagram for the AD7884/AD7885 is shown in
Figure 6. It is set up for an analog input range of ± 5 V. If a ± 3 V
input range is required, A1 should drive ± 3V
IN
S and ± 3V
IN
F
with ± 5V
IN
S, ± 5V
IN
F being tied to system AGND.
3V
IN
F
5V
IN
F
–5V
+5V
AD711, AD845,
OR AD817
AD817
AGNDS
AGNDF
AD7884/
AD7885
AD845, AD817,
OR EQUIVALENT
NOTE: POWER SUPPLY DECOUPLING NOT SHOWN
GND
DGND
V
DD
= +5V
CONTROL
INPUTS
V
INV
V
REF+
S
V
REF+
F
V
REF
3V
IN
S
5V
IN
S
AV
SS
V
DD
AV
DD
V
SS
V
IN
AD780
2
6
8
4
10F
A1
A2
A3
A4
DATA
OUTPUTS
AD845, AD817,
OR EQUIVALENT
Figure 6. AD7884/AD7885 Operational Diagram
The chosen input buffer amplifier (A1) should have low noise and
distortion and fast settling time for high bandwidth applications.
The AD711, AD845, and AD817 are suitable op amps.
A2 is the force, sense amplifier for AGND. The AGNDS pin
should be at zero potential. Therefore, the amplifier must have a
low input offset voltage and good noise performance. It must
also have the ability to deal with fast current transients on the
AGNDS pin. The AD817 has the required performance and is
the recommended amplifier.
If AGNDS and AGNDF are simply tied together to star
ground instead of buffering, the SNR and THD are not signifi-
cantly degraded. However, dc specifications like INL, bipolar
zero, and gain error will be degraded.
REV. E
AD7884/AD7885
–9–
The required 3 V reference is derived from the AD780 and
buffered by the high speed amplifier A3 (AD845, AD817, or
equivalent). A4 is a unity gain inverter that provides the –3 V
negative reference. The gain setting resistors are on-chip and are
factory trimmed to ensure precise tracking of V
REF+
. Figure 6
shows A3 and A4 as AD845s or AD817s. These have the ability to
respond to the rapidly changing reference input impedance.
CIRCUIT DESCRIPTION
Analog Input Section
The analog input section of the AD7884/AD7885 is shown in
Figure 7. It contains both the input signal conditioning and
sample-and-hold amplifier. Note that the analog input is truly
benign. When SW1
A
goes open circuit to put the SHA into the
hold mode, SW1
B
is closed. This means that the input resistors,
R1 and R2, are always connected to either virtual ground or
true ground.
R5
4k
C1
SW1
A
A1
3V
IN
F
TO RESIDUE
AMPLIFIER A2
TO 9-BIT
ADC
V
REF–
SW1
B
R3
3k
R6
2k
R4
4k
R2
5k
R1
3k
3V
IN
S
5V
IN
F
5V
IN
S
A1
Figure 7. AD7884/AD7885 Analog Input Section
When the ± 3V
IN
S and ± 3V
IN
F inputs are tied to 0 V, the
input section has a gain of –0.6 and transforms an input signal of
±5 V to the required ±3 V. When the ±5V
IN
S and ±5V
IN
F inputs
are grounded, the input section has a gain of –1 and so the analog
input range is now ±3 V. Resistors R4 and R5, at the amplifier
output, further condition the ±3 V signal to be 0 V to –3 V. This
is the required input for the 9-bit A/D converter section.
With SW1
A
closed, the output of A1 follows the input (the
sample-and-hold is in the track mode). On the rising edge of
the CONVST pulse, SW1
A
goes open circuit and capacitor C1
holds the voltage on the output of A1. The sample-and-hold is
now in the hold mode. The aperture delay time for the sample-
and-hold is nominally 50 ns.
A/D Converter Section
The AD7884/AD7885 uses a two-pass flash technique in order
to achieve the required speed and resolution. When the CONVST
control input goes from low to high, the sample-and-hold ampli-
fier goes into the hold mode and a 0 V to –3 V signal is presented
to the input of the 9-bit ADC. The first phase of conversion
generates the 9 MSBs of the 16-bit result and transfers these to
the latch and ALU combination. They are also fed back to the
9 MSBs of the 16-bit DAC. The 7 LSBs of the DAC are
permanently loaded with 0s. The DAC output is subtracted from
the analog input with the result being amplified and offset in the
Residue Amplifier section.
The signal at the output of A2 is proportional to the error
between the first phase result and the actual analog input
signal and is digitized in the second conversion phase. This
second phase begins when the 16-bit DAC and the residue
error amplifier have both settled. First, SW2 is turned off and
SW3 is turned on. Then, the SHA section of the residue
amplifier goes into hold mode. Next SW2 is turned off and
SW3 is turned on. The 9-bit result is transferred to the output
latch and ALU. An error correction algorithm now compensates
for the offset inserted in the residue amplifier section and
errors introduced in the first pass conversion and combines both
results to give the 16-bit answer.
9
9
V
REF–
R4
4k
R5
4k
SW2
SW3
R6
2k
A2
9-BIT
ADC
LATCH
+
ALU
16
0 TO –3V
3V SIGNAL
FROM INPUT
SHA
V
REF+
F
R7
2k
R8
2k
+3V –3V
RESIDUE AMP
+ SHA
9
16-BIT
ACCURATE
DAC
V
REF+
S
V
INV
V
REF–
Figure 8. A/D Converter Section
Timing and Control Section
Figure 9 shows the timing and control sequence for the AD7884/
AD7885. When the part receives a CONVST pulse, the con-
version begins. The input sample-and-hold goes into the hold
mode 50 ns after the rising edge of CONVST and BUSY goes
low. This is the first phase of conversion and takes 3.35 µs to
complete. The second phase of conversion begins when SW2 is
turned off and SW3 is turned on. The residue amplifier and
SHA section (A2 in Figure 8) goes into hold mode at this point
and allows the input sample-and-hold to go back into sample
mode. Thus, while the second phase of conversion is ongoing,
the input sample-and-hold is also acquiring the input signal for
the next conversion. This overlap between conversion and
acquisition allows throughput rates of 166 kSPS to be achieved.
CONVST
BUSY
HOLD
SAMPLE
INPUT
SHA
FIRST PHASE
3.5s
TACQ
2.5s
SECOND
PHASE
FIRST PHASE OF CONVERSION
FIRST 9-BIT CONVERSION
DAC SETTLING TIME
RESIDUE AMPLIFIER
SETTLING TIME
SECOND PHASE OF CONVERSION
SECOND 9-BIT CONVERSION
ERROR CORRECTION
OUTPUT LATCH UPDATE
1.8s
Figure 9. Timing and Control Sequence

AD7884BPZ-REEL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16-Bit Monolithic
Lifecycle:
New from this manufacturer.
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