AD5535
Rev. A | Page 15 of 16
Use as large a trace as possible for the supply lines of the device
to provide low impedance paths and reduce the effects of glitches
on the power supply line. Components, such as clocks with fast-
switching signals, should be shielded with digital ground to avoid
radiating noise to other sections of the board. Clock signals
should never be run near the analog inputs of the device. Avoid
crossovers of digital and analog signals. Traces for analog inputs
should be kept as wide and short as possible and should be
shielded with analog ground if possible. Traces on opposite
sides of a 2-layer printed circuit board should run at right
angles to each other to reduce the effects of feedthrough
through the board.
POWER SUPPLY SEQUENCING AND DECOUPLING
RECOMMENDATIONS
The diagram in Figure 23 shows the recommended decoupling
and power supply protection for the AD5535. On the AD5535,
it is recommended to tie all grounds together as close to the device
as possible. If the number of supplies must be reduced, all supplies
should be brought back separately and a provision should be
made on the board via a link option to drive the AV
CC
and V
+
from the same supply. All power supplies should be adequately
decoupled with 10 μF tantalum and 0.1 μF ceramic capacitors.
Note that the capacitors on the V
PP
supply must be rated at
greater than 210 V. To overcome issues associated with power
supply sequencing when using high voltage supplies, the use of
protection diodes as indicated in
A microstrip technique is by far the best, but it is not always
possible to use with a double-sided board. In this technique,
the component side of the board is dedicated to ground planes,
and signals are placed on the solder side. Multilayer printed
circuit boards with dedicated ground, power, and tracking
layers offer the optimum solution in terms of obtaining analog
performance, but at increased manufacturing costs.
Figure 23 is recommended.
AGND
DACGND
DGND
DV
CC
AV
CC
V
PP
PGND
V
–
V
+
AV
CC
= +5V
DV
CC
= +5V
V
PP
= +210V
V
+
= +5V
V
–
= –5V
AD5535
SD103C RS1G
10μF
10μF
0.1μF
0.1μF
0.1μF
10μF
10μF
10μF
0.1μF
0.1μF
HIGH VOLTAGE DIODE
MANUFACTURER: GS
CHOTTKY DIODE
MANUFACTURER: IT
05068-017
Good decoupling is vitally important when using high resolu-
tion converters. All analog supplies should be decoupled with
10 μF tantalum in parallel with 0.1 μF ceramic capacitors to
analog ground. To achieve the best from the decoupling
components, these should be placed as close to the device as
possible, ideally right up against the IC or the IC socket. The
main aim of a bypassing element is to maximize the charge
stored in the bypass loop while simultaneously minimizing the
inductance of this loop. Inductance in the loop acts as an
impedance to high frequency transients and results in power
supply spiking. By keeping the decoupling as close to the device
as possible, the loop area is kept as small as possible, thereby
reducing the possibility of power supply spikes. Digital supplies
of high resolution converters should be decoupled with 10 μF
tantalum and 0.1 μF ceramic to the digital ground plane. The
amplifiers’ V
Figure 23. Recommended Power Supply Sequencing and Decoupling
GUIDELINES FOR PRINTED
CIRCUIT BOARD LAYOUT
Printed circuit boards should be designed such that the analog
and digital sections are separated and confined to designated
analog and digital sections of the board. This facilitates the use
of ground planes that can be separated easily. A minimum etch
technique is generally found to be the best for ground planes
because it optimizes shielding of sensitive signal lines. Digital
and analog ground planes should be joined only in one place, at
the AGND and DGND pins of the high resolution converter.
Data and address buses on the board should be buffered or
latched to isolate the high frequency bus of the processor from
the bus of the high resolution converters. These act as a faraday
shield and increase the signal-to-noise performance of the
converters by reducing the amount of high frequency digital
coupling. Avoid running digital lines under the device because
they couple noise onto the die. The ground plane should be
allowed to run under the IC to avoid noise coupling.
and V
DD SS
supplies should be decoupled with 10 μF
and 0.1 μF to AGND.
All logic chips should be decoupled with 0.1 μF to digital
ground to decouple high frequency effects associated with
digital circuitry.
