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LTC2463CDD#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
LTC2461/LTC2463
10
24613fa
APPLICATIONS INFORMATION
The START and STOP Conditions
A START (S) condition is generated by transitioning SDA
from HIGH to LOW while SCL is HIGH. The bus is consid-
ered to be busy after the START condition. When the data
transfer is finished, a STOP (P) condition is generated by
transitioning SDA from LOW to HIGH while SCL is HIGH.
The bus is free after a STOP is generated. START and STOP
conditions are always generated by the master.
When the bus is in use, it stays busy if a repeated START
(Sr) is generated instead of a STOP condition. The repeated
START timing is functionally identical to the START and
is used for reading from the device before the initiation
of a new conversion.
Data Transferring
After the START condition, the I
2
C bus is busy and data
transfer can begin between the master and the addressed
slave. Data is transferred over the bus in groups of nine
bits, one byte followed by one acknowledge (ACK) bit. The
master releases the SDA line during the ninth SCL clock
cycle. The slave device can issue an ACK by pulling SDA
LOW or issue a Not Acknowledge (NAK) by leaving the
SDA line HIGH impedance (the external pull-up resistor
will hold the line HIGH). Change of data only occurs while
the clock line (SCL) is LOW.
Output Data Format
After a START condition, the master sends a 7-bit address
followed by a read request (R) bit. The bit R is 1 for a
Read Request. If the 7-bit address matches the LTC2461/
LTC2463’s address (0010100 or 1010100, depending on the
state of the pin A0) the ADC is selected. When the device is
addressed during the conversion state, it does not accept
the request and issues a NAK by leaving the SDA line HIGH.
If the conversion is complete, the LTC2461/LTC2463 issue
an ACK by pulling the SDA line LOW.
Following the ACK, the LTC2461/LTC2463 can output data.
The data output stream is 16 bits long and is shifted out
on the falling edges of SCL (see Figure 5a).
The DATA INPUT/OUTPUT state is concluded once all 16
data bits have been read or after a STOP condition.
The LTC2463 (differential input) output code is given by
32768 • (V
IN
+
– V
IN
–
)/V
REF
+ 32768. The first bit output
by the LTC2463, D15, is the MSB, which is 1 for V
IN
+
≥
V
IN
–
and 0 for V
IN
+
< V
IN
–
. This bit is followed by succes-
sively less significant bits (D14, D13, …) until the LSB is
output by the LTC2463, see Table 1.
The LTC2461 (single-ended input) output code is a direct
binary encoded result, see Table 1.
1 7 8 9 2 31 8
D8D13D14
MSB
D15RSDA
SCL
7-BIT
ADDRESS
START BY
MASTER
D7 D6 D5 D0
LSB
9 1 2 3 8 9
ACK BY
MASTER
NACK BY
MASTER
SLEEP DATA OUTPUT CONVERSION
24613 F05a
ACK BY
LTC2461/LTC2463
Figure 5a. Read Sequence Timing Diagram
LTC2461/LTC2463
11
24613fa
APPLICATIONS INFORMATION
Data Input Format
After a START condition, the master sends a 7-bit ad-
dress followed by a read/write request (R/W) bit. The
R/W bit is 0 for a write. The data input word is 4 bits long
and consists of two enable bits (EN1 and EN2) and two
programming bits (SPD and SLP), see Figure 5b. EN1 is
applied to the first rising edge of SCL after a valid write
address is acknowledged. Programming is enabled by
setting EN1 = 1 and EN2 = 0.
The speed bit (SPD) is only used by the LTC2461. In the
default mode, SPD = 0, the output rate is 60Hz and con-
tinuous background offset calibration is not performed. By
changing the SPD bit to 1, background offset calibration
is performed and the output rate is reduced to 30Hz. The
LTC2463 data output rate is always 60Hz and background
offset calibration is performed (SPD = don’t care).
The sleep bit (SLP) is used to power down the on chip
reference. In the default mode, the reference remains
powered up even when the ADC is powered down. If the
SLP bit is set HIGH, the reference will power down after
the next conversion is complete. It will remain powered
down until a valid address is acknowledged. The reference
startup time is approximately 12ms. In order to ensure a
stable reference for the following conversions, either the
data input/output time should be delayed 12ms after an
address acknowledge or the first conversion following a
reference start up should be discarded.
Figure 5b. Timing Diagram for Writing to the LTC2461/LTC2463
SDA
SCL
EN1 EN2 SPD SLP
W
SLEEP
START BY
MASTER
DATA INPUT
7 8 9
1 2 3 4 5 6 7 8 9
1 2 …
7-BIT ADDRESS
ACK BY
LTC2461/LTC2463
ACK BY
LTC2461/LTC2463
24613 F03
Table 1. LTC2461/LTC2463 Output Data Format
SINGLE ENDED INPUT V
IN
(LTC2461)
DIFFERENTIAL INPUT VOLTAGE
V
IN
+
– V
IN
–
(LTC2463)
D15
(MSB)
D14 D13 D12...D2 D1 D0
(LSB)
CORRESPONDING
DECIMAL VALUE
≥V
REF
≥V
REF
1 1 1 1 1 1 65535
V
REF
– 1LSB V
REF
– 1LSB 1 1 1 1 1 0 65534
0.75 • V
REF
0.5 • V
REF
1 1 0 0 0 0 49152
0.75 • V
REF
– 1LSB 0.5 • V
REF
– 1LSB 1 0 1 1 1 1 49151
0.5 • V
REF
0 1 0 0 0 0 0 32768
0.5 • V
REF
– 1LSB –1LSB 0 1 1 1 1 1 32767
0.25 • V
REF
–0.5 • V
REF
0 1 0 0 0 0 16384
0.25 • V
REF
– 1LSB –0.5 • V
REF
– 1LSB 0 0 1 1 1 1 16383
0 ≤ –V
REF
0 0 0 0 0 0 0
LTC2461/LTC2463
12
24613fa
Figure 7b. Start a New Conversion without Reading Old Conversion Result
Figure 7c. Synchronize the LTC2461/LTC2463 with the Global Address Call
SLEEP
S PR ACK READ (OPTIONAL)
DATA OUTPUT CONVERSIONCONVERSION
24613 F07a
7-BIT ADDRESS
(0010100 OR 1010100)
APPLICATIONS INFORMATION
Figure 6. Consecutive Reading
SLEEP SLEEP
S PR ACK READ READ
DATA OUTPUT
CONVERSION CONVERSION
24613 F06
S R PACK
CONVERSIONDATA OUTPUT
7-BIT ADDRESS
(0010100 OR 1010100)
7-BIT ADDRESS
(0010100 OR 1010100)
OPERATION SEQUENCE
Continuous Read
Conversions from the LTC2461/LTC2463 can be continu-
ously read, see Figure 6. The R/W is 1 for a read. At the
end of a read operation, a new conversion automatically
begins. At the conclusion of the conversion cycle, the next
result may be read using the method described above. If
the conversion cycle is not complete and a valid address
selects the device, the LTC2461/LTC2463 generate a NAK
signal indicating the conversion cycle is in progress. See
Figure 7a for an example state diagram.
Discarding a Conversion Result and Initiating a New
Conversion
It is possible to start a new conversion without reading
the old result, as shown in Figure 7b. Following a valid
7-bit address, a read request (R/W) bit, and a valid ACK,
a STOP command will start a new conversion.
Synchronizing the LTC2461/LTC2463 with the
Global Address Call
The LTC2461/LTC2463 can also be synchronized with
the global address call (see Figure 7c). To achieve this,
the LTC2461/LTC2463 must first have completed the
Figure 7a. I
2
C State Diagram
24613 F07b
7-BIT ADDRESS:
0010100 OR 1010100
WRITE INPUT
CONFIGURATION
(FIGURE 5b)
FOR CYCLE N
I
2
C START
R/W
BIT LOW
WRITE INPUT
CONFIGURATION
(FIGURE 5b)
I
2
C STOP CONVERT
CONVERSION
FINISHED
ACK
ACK
ACK
NAK
I
2
C (REPEAT) START
R/W
BIT LOW
7-BIT ADDRESS:
0010100 OR 1010100
I
2
C START
R/W
BIT HIGH
READ DATA FROM
CYCLE N-1
I
2
C STOP CONVERT
CONVERSION
FINISHED
7-BIT ADDRESS:
0010100 OR 1010100
GLOBAL ADDRESS
(1110111)
SLEEP
CONVERSION
S W ACK WRITE (OPTIONAL) P
24613 F07c
DATA INPUT
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

LTC2463CDD#PBF

Mfr. #:
Buy LTC2463CDD#PBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16-Bit I2C 60Hz Differential Delta Sigma ADC with Internal Reference
Lifecycle:
New from this manufacturer.
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