TDA3683J/N2S,112 Datasheet TDA3683J/N2S,112, TDA3683J/N2C,112, TDA3683SD/N2C,112 | P7-P9

Product data sheet Rev. 02 — 7 October 2005 7 of 31

Philips Semiconductors

TDA3683

Multiple voltage regulator with switch and ignition buffer

7.3 Power switch

The power switch (pin PSW) is activated by the MODE input. It is switched off during

thermal shutdown and load dump conditions. The power switch output voltage is internally

clamped at 16 V to protect connected application circuitry (e.g. display and CD / tape

drives). The power switch has three different output current modes, depending on its

output voltage, the reset capacitor (RDC1) and the junction temperature (i.e. high current,

low current and foldback protection); see Figure 7. In the event of an overload the power

switch can maintain the maximum output current for a limited period of time (determined

by the integration time of the reset delay capacitor) before it drops back to the lower output

current capability. This functionality is implemented to prevent, in case of loads such as

light bulbs, relays or electrical motors, the power switch from folding back on momentary

high inrush currents. In the event of junction temperatures above 150 °C, the power switch

will drop back to the lower output current capability.The power switch has a built-in ﬂyback

clamp for use in case of inductive loads.

7.4 Enable and mode inputs

The enable inputs (pins EN1 and EN2/3) are used to switch on or switch off the standby

regulators. The mode input (MODE) is used to enable the switched regulators and the

power switch. When all of these inputs are LOW the circuit is in Sleep mode and only the

enable detection circuit and the supply overvoltage protection circuit are active. In Sleep

mode the device draws a very small quiescent current from the supply. When at least one

of the enable inputs is activated the circuit will operate in Standby mode. When the mode

input is activated the on condition will be established; before the MODE pin can be

activated at least one of the standby regulators must be activated. The enable and mode

inputs are 3.3 V and 5 V CMOS logic compatible. A detailed description of the enable and

mode pin dependencies is given in Table 4.

Table 4: Enable and mode pin dependencies

Pin Description

EN1 EN2/3 MODE

0 0 0 standby regulators, switched regulators, power switch and

ignition buffer disabled

0 0 1 standby regulators, switched regulators, power switch and

ignition buffer disabled

0 1 0 standby regulators 2 and 3 and ignition buffer enabled; standby

regulator 1, switched regulators and power switch disabled

0 1 1 standby regulators 2 and 3, switched regulators and ignition

buffer enabled; standby regulator 1 and power switch disabled

1 0 0 standby regulator 1 and ignition buffer enabled; standby

regulators 2 and 3, switched regulators and power switch

disabled

1 0 1 standby regulator 1, switched regulators, power switch and

ignition buffer enabled; standby regulators 2 and 3 disabled

1 1 0 standby regulators and ignition buffer enabled; switched

regulators and power switch disabled

1 1 1 standby regulators, ignition buffer, switched regulators and

power switch enabled

Product data sheet Rev. 02 — 7 October 2005 8 of 31

Philips Semiconductors

TDA3683

Multiple voltage regulator with switch and ignition buffer

7.5 Storage capacitor

The storage capacitor (pin STC) is used as a back-up supply for the standby regulators

when the battery (pins V

/ V

) can no longer provide the supply. This situation may

occur for cold weather engine starts. The rising and falling storage capacitor voltage

threshold levels determine if the standby regulators can be switched on.

The storage capacitor pin is not intended to be used as an output (e.g. supply switch). No

external load should be connected to this pin.

7.6 Reset delay capacitors

The reset delay capacitors (pins RDC1 and RDC2/3) are used to delay the reset pulse

(RST1 and RST2/3) starting from the time the associated standby regulator output voltage

comes within its regulated voltage range i.e. crosses the rising reset threshold level. An

internal current source is used to charge the reset delay capacitor. The reset output will be

released (output goes HIGH) when the voltage on the reset delay capacitor crosses the

rising threshold level.

If the associated standby regulator voltage drops out of its regulated voltage range (drops

below its falling reset threshold level) the reset delay capacitor will be discharged with a

relatively high sink current. The reset output will be activated (output goes LOW) when the

reset delay capacitor crosses the falling threshold level. This feature is included to secure

a smooth start-up of the microcontroller at ﬁrst connection, without uncontrolled switching

of the relevant standby regulators during a start-up sequence. It should be noted that

RDC1 is also used as a time constant for the delayed current protection of the power

switch.

7.7 Reset outputs

The reset function depends on the reset delay capacitor voltage and includes hysteresis

to avoid oscillation at the threshold level. The reset outputs are push-pull for sourcing or

sinking current. The output voltage can be switched between the ground level and the

output voltage of the relevant standby regulator. An external reset delay capacitor can be

added if a timed reset pulse is required (C

RDC1

or C

RDC2/3

Standby regulator 1 has an independent reset function (pins RST1 and RDC1). Standby

regulators 2 and 3 have combined circuitry (pins RST2/3 and RDC2/3). The reset trigger

signals from both regulators are connected using an OR function to the reset output buffer

thus ensuring that both regulators can generate a reset when appropriate. The RST1

output is linked to standby regulator 1 (5 V) and, therefore, generates a 5 V HIGH-level

output voltage. The RST2/3 output is linked to regulator 2 (3.3 V) and, therefore,

generates a 3.3 V HIGH-level output voltage.

7.8 Hold output

The hold output (pin HOLD) is a combined output for the thermal pre-warning signal and

all other diagnostic signals. To distinguish between these signals, the HOLD output is

designed as an active HIGH 3-state output buffer. When a no failure condition is present

the output is LOW. When a thermal pre-warning signal is generated (e.g. to shut down

other circuits in the radio before the regulator itself shuts down) the signal rises to its MID

Product data sheet Rev. 02 — 7 October 2005 9 of 31

Philips Semiconductors

TDA3683

Multiple voltage regulator with switch and ignition buffer

level. In all other warning situations, the HOLD output rises to its HIGH level. In order to

generate standard CMOS logic compliant signals an external decoding circuit has to be

implemented; see Figure 9.

The HOLD output will be active HIGH when:

• The output voltage of one or more switched regulators is out of regulation (except

REG7), due to overload or supply voltage drops

• The power switch operates in the Foldback mode

• In Standby or On mode the thermal shutdown is activated

• In Standby or On mode the load dump protection is activated

• In Standby mode a low battery voltage occurs (V

) indicating that it is not possible to

pull REG4 into regulation when switching it on.

It should be noted that there is intentionally no out-of-regulation detection for REG7 since

it can be adjusted to maximum 10 V and would, in that event, activate the HOLD signal

very early.

The HOLD function includes hysteresis in order to avoid oscillations when the hold

threshold level is crossed. A schematic diagram of the HOLD function is illustrated in

Figure 3.

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TDA3683J/N2S,112

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Buy TDA3683J/N2S,112

Manufacturer:

NXP Semiconductors

Description:

Linear Voltage Regulators MULT VLTG REGULATOR SWITCH/IGNITION BUFF

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TDA3683J/N2S,112

TDA3683J/N2S,112

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