NB4N121KMNG

© Semiconductor Components Industries, LLC, 2012
April, 2012 Rev. 6
1 Publication Order Number:
NB4N121K/D
NB4N121K
3.3V Differential 1:21
Differential Fanout Clock
Driver with HCSL level
Output
Description
The NB4N121K is a Clock differential input fanout distribution 1 to
21 HCSL level differential outputs, optimized for ultra low
propagation delay variation. The NB4N121K is designed with HCSL
clock distribution for FBDIMM applications in mind.
Inputs can accept differential LVPECL, CML, or LVDS levels.
Singleended LVPECL, CML, LVCMOS or LVTTL levels are
accepted with the proper V
REFAC
supply (see Figures 5, 10, 11, 12,
and 13). Clock input pins incorporate an internal 50 W on die
termination resistors.
Output drive current at I
REF
(Pin 1) for 1X load is selected by
connecting to GND. To drive a 2X load, connect I
REF
to V
CC
. See
Figure 9.
The NB4N121K specifically guarantees low output–to–output
skews. Optimal design, layout, and processing minimize skew within
a device and from device to device. System designers can take
advantage of the NB4N121K’s performance to distribute low skew
clocks across the backplane or the motherboard.
Features
Typical Input Clock Frequency 100, 133, 166, 200, 266, 333 and
400 MHz
340 ps Typical Rise and Fall Times
800 ps Typical Propagation Delay
Dtpd 100 ps Maximum Propagation Delay Variation Per Each
Differential Pair
Additive Phase RMS Jitter: 1 ps Max
Operating Range: V
CC
= 3.0 V to 3.6 V with V
EE
= 0 V
Differential HCSL Output Level (700 mV PeaktoPeak)
PbFree Packages are Available
A = Assembly Site
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
QFN52
MN SUFFIX
CASE 485M
MARKING DIAGRAM*
http://onsemi.com
NB4N
121K
AWLYYWWG
1
52
Figure 1. Pin Configuration (Top View)
Q0
Q0
Q1
Q1
Q19
Q19
Q20
Q20
CLK
CLK
V
CC
GND
R
REF
I
REF
See detailed ordering and shipping information in the
package dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
VTCLK
VTCLK
152
NB4N121K
http://onsemi.com
2
Figure 2. Pinout Configuration (Top View)
VCC
Q0
Q1
Q1
Q2
Q2
Q3
Q4
Q4
I
REF
VCC
Q6
Q3
Q5
Q5
GND
Q20
Q8
Q9
Q11
Q11
Q17
Q14
Q13
Q14
Q13
Q16
1
2
3
4
5
6
7
8
9
10
11
12
13
VTCLK
CLK
CLK
VTCLK
V
CC
Q20
Q19
Q19
Q18
Q18
14
15
16
17
18
19
20
21
22
23
24
25
26
Q17
Q16
Q15
Q15
Q12
Q12
VCC
39
38
37
36
35
34
33
32
31
30
29
28
27
Q10
Q10
Q9
Q8
Q7
Q7
Q6
52
51
50
49
48
47
46
45
44
43
42
41
40
Q0
Exposed Pad (EP)
NB4N121K
Table 1. PIN DESCRIPTION
Pin Name I/O Description
1 I
REF
Output Output current programming pin to select load drive. For 1X
configuration, connect I
REF
to GND, or for 2X configuration, connect
I
REF
to V
CC
(See Figure 9).
2 GND Supply Ground. GND pin must be externally connected to power supply
to guarantee proper operation.
3, 6 VTCLK,
VTCLK
Internal 50 W Termination Resistor connection Pins. In the differential
configuration when the input termination pins are connected to the com-
mon termination voltage, and if no signal is applied then the device may
be susceptible to selfoscillation.
4 CLK LVPECL Input CLOCK Input (TRUE)
5 CLK LVPECL Input CLOCK Input (INVERT)
7, 26, 39, 52 V
CC
Positive Supply pins. V
CC
pins must be externally connected to a power
supply to guarantee proper operation.
8, 10, 12, 14, 16, 18, 20, 22,
24, 27, 29, 31, 33, 35, 37, 40,
42, 44, 46, 48, 50
Q[200] HCSL Output Output (INVERT)
9, 11, 13, 15, 17, 19, 21, 23,
25, 28, 30, 32, 34, 36, 38, 41,
43, 45, 47, 49, 51
Q[200] HCSL Output Output (TRUE)
Exposed Pad EP GND Exposed Pad. The thermally exposed pad (EP) on package bottom (see
case drawing) must be attached to a sufficient heatsinking conduit for
proper thermal operation. (Note 1)
1. The exposed pad must be connected to the circuit board ground.
NB4N121K
http://onsemi.com
3
Table 2. ATTRIBUTES
Characteristic Value
Input Default State Resistors None
ESD Protection Human Body Model
Machine Model
>2 kV
400 V
Moisture Sensitivity (Note 2) QFN52 Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 @ 0.125 in
Transistor Count 622
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS (Note 3)
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
Positive Power Supply GND = 0 V 4.6 V
V
I
Positive Input GND = 0 V GND 0.3 v V
I
v V
CC
V
V
INPP
Differential Input Voltage |CLK CLKb| V
CC
V
I
OUT
Output Current Continuous
Surge
50
100
mA
mA
T
A
Operating Temperature Range QFN52 40 to +70 °C
T
stg
Storage Temperature Range 65 to +150 °C
q
JA
Thermal Resistance (JunctiontoAmbient) (Note 3) 0 lfpm
500 lfpm
QFN52
QFN52
25
19.6
°C/W
°C/W
q
JC
Thermal Resistance (JunctiontoCase) 2S2P (Note 4) QFN52 21 °C/W
T
sol
Wave Solder PbFree 265 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard 516, multilayer board 2S2P (2 signal, 2 power).
4. JEDEC standard multilayer board 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.

NB4N121KMNG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Buffer UTL TSMC 1:21 FANOUT HCSL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet