NB4N121KMNG

NB4N121K
http://onsemi.com
4
Table 4. DC CHARACTERISTICS (V
CC
= 3.0 V to 3.6 V, T
A
= 40°C to +70°C Note 5)
Symbol
Characteristic Min Typ Max Unit
I
GND
GND Supply Current (All Outputs Loaded) 70 98 120 mA
I
CC
Power Supply Current (All Outputs Loaded) 1X
2X
420
780
mA
I
IH
Input HIGH Current CLKx, CLKx 2.0 150
mA
I
IL
Input LOW Current CLKx, CLKx 150 2.0
mA
DIFFERENTIAL INPUT DRIVEN SINGLEENDED (Figures 5 and 7)
V
th
Input Threshold Reference Voltage Range (Note 6) 1050 V
CC
150 mV
V
IH
SingleEnded Input HIGH Voltage V
th
+ 150 V
CC
mV
V
IL
SingleEnded Input LOW Voltage GND V
th
150 mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 6 and 8)
V
IHD
Differential Input HIGH Voltage 1200 V
CC
mV
V
ILD
Differential Input LOW Voltage GND V
CC
75 mV
V
ID
Differential Input Voltage (V
IHD
V
ILD
) 75 2400 mV
V
CMR
Input Common Mode Range 1163 V
CC
75
HCSL OUTPUTS (Figure 4)
V
OH
Output HIGH Voltage 600 740 900 mV
V
OL
Output LOW Voltage 150 0 150 mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input parameters vary 1:1 with V
CC
. Measurements taken with outputs in either 1X (all outputs loaded 50 W to GND) or 2X (all outputs loaded
25 W to GND) configuration, see Figure 9. For 1X configuration, connect
IREF
to GND, or for 2X configuration, connect
IREF
to V
CC
.
6. V
th
is applied to the complementary input when operating in single ended mode.
NB4N121K
http://onsemi.com
5
Table 5. AC CHARACTERISTICS V
CC
= 3.0 V to 3.6 V, GND = 0 V; 40°C to +70°C (Note 7)
Symbol
Characteristic Min Typ Max Unit
V
OUTPP
Output Voltage Amplitude (@ V
INPPmin
) f
in
= 133 MHz
f
in
= 166 MHz
f
in
= 200 MHz
725
725
725
900
900
900
mV
t
PLH
,
t
PHL
Propagation Delay to (See Figure 3) CLK/CLK to Qx/Qx 550 800 950 ps
Dt
PLH
,
Dt
PHL
Propagation Delay Variations Variation Per Each Diff Pair CLK/CLK to Qx/Qx
(Note 8) (See Figure 3)
100 ps
t
SKEW
Duty Cycle Skew (Note 9)
WithinDevice Skew, 1X Mode Only (Note 10)
WithinDevice Skew, 2X Mode (Note 10)
DevicetoDevice Skew (Note 10)
20
50
80
150
ps
ps
ps
ps
t
jit(
f
)
Additive RMS Phase RMS (Note 11) f
in
=133 MHz to 200 MHz 1 ps
V
cross
Absolute Crossing Magnitude Voltage 250 550 mV
DV
cross
Variation in Magnitude of V
cross
150 mV
t
r
, t
f
Absolute Magnitude in Output Risetime and Falltime Qx, Qx
(From 175 mV to 525 mV)
175 340 700 ps
Dt
r,
Dt
f
Variation in Magnitude of Risetime and Falltime (SingleEnded) Qx, Qx
(See Figure 4)
1X
2X
125
150
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Measured by forcing V
INPP
(MIN) from a 50% duty cycle clock source. Measurements taken with outputs in either 1X (all outputs loaded
50 W to GND) or 2X (all outputs loaded 25 W to GND) configuration, see Figure 9. For 1X configuration, connect I
REF
to GND, or for 2X
configuration, connect I
REF
to V
CC
. Typical gain is 20 dB.
8. Measured from the input pair crosspoint to each single output pair crosspoint across temp and voltage ranges.
9. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw and Tpw+.
10.Skew is measured between outputs under identical transition @ 133 MHz.
11. Additive RMS jitter with 50% duty cycle clock signal using phase noise integrated from 12 KHz to 33 MHz
Figure 3. AC Reference Measurement
CLK
CLK
Q
Q
t
PLH
t
PHL
V
INPP
= V
IH
(CLK) V
IL
(CLK)
= V
IH
(CLK) V
IL
(CLK)
V
OUTPP
= V
OH
(Q) V
OL
(Q)
= V
OH
(Q) V
OL
(Q)
Dt
PLH
Dt
PHL
NB4N121K
http://onsemi.com
6
Figure 4. HCSL Output Parameter Characteristics
525 mV
DV
CROSS
V
CROSS
175 mV
t
r
t
f
CLK
V
th
CLK
V
th
Figure 5. Differential Input Driven
SingleEnded (V
th
= V
REFAC
)
CLK
CLK
Figure 6. Differential Inputs Driven
Differentially
V
IHmax
V
ILmax
V
IH
V
th
V
IL
V
IHmin
V
ILmin
V
CC
V
thmax
V
thmin
GND
V
th
V
IHDmax
V
ILDmax
V
IHDmin
V
ILDmin
V
IHDtyp
V
ILDtyp
V
ID
= V
IHD
V
ILD
V
CMR
V
CC
V
CMmax
V
CMmin
GND
Figure 7. V
th
Diagram Figure 8. V
CMR
Diagram

NB4N121KMNG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Buffer UTL TSMC 1:21 FANOUT HCSL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet