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ST16C452IJ68-F

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13
ST16C452/452PS
Rev. 3.20
REGISTER FUNCTIONAL DESCRIPTIONS
The following table delineates the assigned bit functions for the eighteen 452/452PS internal registers. The
assigned bit functions are more fully defined in the following paragraphs.
Table 7, ST16C452/452PS INTERNAL REGISTERS
A2 A1 A0 Register BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0
[Default]
Note 5*
General Register Set: Note 1*
0 0 0 RHR [XX] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
0 0 0 THR [XX] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
0 0 1 IER [00] 0000Modem Receive Transmit Receive
Status Line Holding Holding
Interrupt Status Register Register
interrupt interrupt
0 1 0 ISR [01] 0000INTINTINTINT
priority priority priority status
bit-2 bit-1 bit-0
0 1 1 LCR [00] divisor set set even parity stop word word
latch break parity parity enable bits length length
enable bit-1 bit-0
1 0 0 MCR [00] 0 0 0 loop INT A/B [X] -RTS -DTR
back enable
1 0 1 LSR [60] 0 THR & THR. break framing parity overrun receive
TSR empty interrupt error error error data
empty ready
1 1 0 MSR [X0] CD RI DSR CTS delta delta delta delta
-CD -RI -DSR -CTS
1 1 1 SPR [FF] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
Special Register Set: Note *2
0 0 0 DLL [XX] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
0 0 1 DLM [XX] bit-15 bit-14 bit-13 bit-12 bit-11 bit-10 bit-9 bit-8
14
ST16C452/452PS
Rev. 3.20
A2 A1 A0 Register BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0
[Default]
Note 5*
Printer Port Register Set: Note 3*
[X] 0 0 PR[00] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
[X] 0 0 PR[00] bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
[X] 0 1 SR[4F] -Busy -ACK PE SLCT Error -IRQ logic logic
State “1” “1”
[X] 0 1 IOSEL bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0
[X] 1 0 COM[E0] logic logic logic -INTP -SLCTIN INIT -Auto -STROBE
“1” “1” “1” Enable FDXT
[X] 1 0 CON[00] [X] [X] PD 0-7 -INTP -SLCTIN INIT -Auto -STROBE
IN/OUT Enable FDXT
Note 1* The General Register set is accessible only when CS A or CS B is a logic 0.
Note 2* The Baud Rate register set is accessible only when CS A or CS B is a logic 0 and LCR bit-7 is a logic 1.
Note 3*: Printer Port Register set is accessible only when -CSP is a logic 0 in conjunction with the states of the
interface signal BIDEN and Printer Control Register bit-5 or IOSEL register.
Note 5*
The value between the square brackets represents the register’s initialized HEX value, X = N/A.
UART REGISTER DESCRIPTIONS
Transmit (THR) and Receive (RHR) Holding Reg-
isters
The serial transmitter section consists of an 8-bit
Transmit Hold Register (THR) and Transmit Shift
Register (TSR). The status of the THR is provided in
the Line Status Register (LSR). Writing to the THR
transfers the contents of the data bus (D7-D0) to the
THR, providing that the THR or TSR is empty. The
THR empty flag in the LSR register will be set to a logic
1 when the transmitter is empty or when data is
transferred to the TSR. Note that a write operation can
be performed when the transmit holding register
empty flag is set (logic 0 = Buffer full).
The serial receive section also contains an 8-bit
Receive Holding Register, RHR. Receive data is
removed from the 452/452PS by reading the RHR
register. The receive section provides a mechanism to
prevent false starts. On the falling edge of a start or
false start bit, an internal receiver counter starts
counting clocks at the 16x clock rate. After 7 1/2 clocks
the start bit time should be shifted to the center of the
start bit. At this time the start bit is sampled and if it is
still a logic 0 it is validated. Evaluating the start bit in
this manner prevents the receiver from assembling a
false character. Receiver status codes will be posted
in the LSR.
15
ST16C452/452PS
Rev. 3.20
IER BIT-3:
Logic 0 = Disable the modem status register interrupt.
(normal default condition)
Logic 1 = Enable the modem status register interrupt.
IER BIT 4-7:
Not Used - initialized to a logic 0.
Interrupt Status Register (ISR)
The 452/452PS provides four levels of prioritized
interrupts to minimize external software interaction.
The Interrupt Status Register (ISR) provides the user
with four interrupt status bits. Performing a read cycle
on the ISR will provide the user with the highest
pending interrupt level to be serviced. No other inter-
rupts are acknowledged until the pending interrupt is
serviced. Whenever the interrupt status register is
read, the interrupt status is cleared. However it should
be noted that only the current pending interrupt is
cleared by the read. A lower level interrupt may be
seen after rereading the interrupt status bits. The
Interrupt Source Table 8 (below) shows the data
values (bits 0-3) for the four prioritized interrupt levels
and the interrupt sources associated with each of
these interrupt levels:
Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the inter-
rupts from receiver ready, transmitter empty, line
status and modem status registers. These interrupts
would normally be seen on the INT A,B output pins.
IER BIT-0:
This interrupt will be issued when the RHR is full or is
cleared when the RHR is empty.
Logic 0 = Disable the receiver ready interrupt. (normal
default condition)
Logic 1 = Enable the receiver ready interrupt.
IER BIT-1:
This interrupt will be issued whenever the THR is
empty and is associated with bit-1 in the LSR register.
Logic 0 = Disable the transmitter empty interrupt.
(normal default condition)
Logic 1 = Enable the transmitter empty interrupt.
IER BIT-2:
This interrupt will be issued whenever a fully as-
sembled receive character is transferred from the
RSR to the RHR, i.e., data ready, LSR bit-0.
Logic 0 = Disable the receiver line status interrupt.
(normal default condition)
Logic 1 = Enable the receiver line status interrupt.
Table 8, INTERRUPT SOURCE TABLE
Priority [ISR BITS]
Level Bit-3 Bit-2 Bit-1 Bit-0 Source of the interrupt
1 0110LSR (Receiver Line Status Register)
2 0100RXRDY (Received Data Ready)
3 0010TXRDY (Transmitter Holding Register Empty)
4 0000MSR (Modem Status Register)
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ST16C452IJ68-F

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Buy ST16C452IJ68-F
Manufacturer:
MaxLinear
Description:
UART Interface IC DUAL UART W/PARALEL PRINTER PORT
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New from this manufacturer.
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