18
ST16C452/452PS
Rev. 3.20
LSR BIT-3:
Logic 0 = No framing error. (normal default condition)
Logic 1 = Framing error. The receive character did not
have a valid stop bit(s).
LSR BIT-4:
Logic 0 = No break condition. (normal default condi-
tion)
Logic 1 = The receiver received a break signal (RX
was a logic 0 for one character frame time).
LSR BIT-5:
This bit indicates that the 452/452PS is ready to
accept new characters for transmission. This bit
causes the 452/452PS to issue an interrupt to the CPU
when the transmit holding register is empty and the
interrupt enable is set.
Logic 0 = Transmit holding register is not empty.
(normal default condition)
Logic 1 = Transmit holding register is empty. When
this bit is a logic 1, the CPU can load new character
into the Transmit Holding Register for transmission.
LSR BIT-6:
Logic 0 = Transmitter holding and shift registers are
full.
Logic 1 = Transmitter holding and shift registers are
empty (normal default condition).
LSR BIT-7:
Not Used - initialized to a logic 0.
Modem Status Register (MSR)
This register provides the current state of the control
interface signals from the modem, or other peripheral
device that the 452/452PS is connected to. Four bits
of this register are used to indicate the changed
information. These bits are set to a logic 1 whenever
a control input from the modem changes state. These
bits are set to a logic 0 whenever the CPU reads this
register.
MSR BIT-0:
Logic 0 = No -CTS Change (normal default condition)
Logic 1 = The -CTS input to the 452/452PS has
changed state since the last time it was read. A modem
Status Interrupt will be generated.
MSR BIT-1:
Logic 0 = No -DSR Change. (normal default condition)
Logic 1 = The -DSR input to the 452/452PS has
changed state since the last time it was read. A
modem Status Interrupt will be generated.
MSR BIT-2:
Logic 0 = No -RI Change. (normal default condition)
Logic 1 = The -RI input to the 452/452PS has changed
from a logic 0 to a logic 1. A modem Status Interrupt
will be generated.
MSR BIT-3:
Logic 0 = No -CD Change. (normal default condition)
Logic 1 = Indicates that the -CD input to the has
changed state since the last time it was read. A
modem Status Interrupt will be generated.
MSR BIT-4:
Normally MSR bit-4 bit is the compliment of the -CTS
input. However in the loop-back mode, this bit is
equivalent to the RTS bit in the MCR register.
MSR BIT-5:
DSR (active high, logical 1). Normally this bit is the
compliment of the -DSR input. In the loop-back mode,
this bit is equivalent to the DTR bit in the MCR register.
MSR BIT-6:
RI (active high, logical 1). Normally this bit is the
compliment of the -RI input. In the loop-back mode
this bit is equivalent to MCR bit-2 in the MCR register.
MSR BIT-7:
CD (active high, logical 1). Normally this bit is the
compliment of the -CD input. In the loop-back mode
this bit is equivalent to MCR bit-3 in the MCR register.
Note: Whenever any MSR bit 0-3: is set to logic “1”, a
MODEM Status Interrupt will be generated.
