ST16C452IJ68-F Datasheet ST16C452CJ68TR-F, ST16C452IJ68PS-F, ST16C452CJ68-F | P7-P9

ST16C452/452PS

Rev. 3.20

Symbol Pin Signal Type Pin Description

individual UART channels, A through B. A logic 0 on this pin(s)

indicates the modem has received a ringing signal from the

telephone line(s). A logic 1 transition on this input pin will

generate an interrupt for the ringing channel(s). This pin does

not have any effect on the transmit or receive operation.

-RTS A/B 24,12 O Request to Send (active low) - These outputs are associated

with individual UART channels, A through B. A logic 0 on the

-RTS pin(s) indicates the transmitter has data ready and

waiting to send for the given channel(s). Writing a logic 1 in

the modem control register (MCR bit-1) will set this pin to a

logic 0 indicating data is available. After a reset this pin will

be set to a logic 1. This pin does not have any effect on the

transmit or receive operation.

RX A/B 41,62 I Receive Data Input, RX A-B. - These inputs are associated

with individual serial channel(s) to the 452. The RX signal

will be a logic 1 during reset, idle (no data), or when the

transmitter is disabled. During the local loop-back mode,

the RX input pins are disabled and TX data is internally

connected to the UART RX Inputs, internally.

TX A/B 26,10 O Transmit Data, TX A-B - These outputs are associated with

individual serial transmit channel(s) from the 452/452PS.

The TX signal will be a logic 1 during reset, idle (no data),

or when the transmitter is disabled. During the local loop-

back mode, the TX output pins are disabled and TX data is

internally connected to the UART RX Inputs.

SYMBOL DESCRIPTION

ST16C452/452PS

Rev. 3.20

GENERAL DESCRIPTION

The 452/452PS provides serial asynchronous receive

data synchronization, parallel-to-serial and serial-to-

parallel data conversions for both the transmitter and

receiver sections. These functions are necessary for

converting the serial data stream into parallel data that

is required with digital data systems. Synchronization

for the serial data stream is accomplished by adding

start and stops bits to the transmit data to form a data

character (character orientated protocol). Data integ-

rity is insured by attaching a parity bit to the data

character. The parity bit is checked by the receiver for

any transmission bit errors. The electronic circuitry to

provide all these functions is fairly complex especially

when manufactured on a single integrated silicon

chip. The 452/452PS represents such an integration

with greatly enhanced features. The 452/452PS is

fabricated with an advanced CMOS process.

The 452/452PS combines the package functions of a

dual UART and a printer interface on a single inte-

grated chip. The 452/452PS UART is indented to be

software compatible with the ST16C450, and

NS16C450 while the bi-directional printer interface

mode is intended to operate with a CENTRONICS

type parallel printer. However, the printer interface is

designed such that it may be configured to operate

with other parallel printer interfaces or used as a

general purpose parallel interface. The 452 is avail-

able in two versions, the ST16C452 and the

ST16C452PS. The ST16C452 provides single hard-

ware pin to control the printer port data direction while

the 452PS provides an additionally software control

bit to control the printer port data direction to become

compatible PS/2 operating system.

The 452/452PS is capable of operation to 1.5Mbps

with a 24 MHz external clock input. With an external

clock input of 1.8432 MHz the user can select data

rates up to 115.2 Kbps.

FUNCTIONAL DESCRIPTIONS

Functional Modes

Two functional user modes are selectable for the 452/

452PS package. The first of these provides the dual

UART functions, while the other provides the func-

tions of a parallel printer interface. These features are

available through selection at the package interface

select pins.

UART A-B Functions

The UART mode provides the user with the capability

to transfer information between an external CPU and

the 452/452PS package. A logic 0 on chip select pins

-CSA or -CSB allows the user to configure, send data,

and/or receive data via the UART channels A-B.

Printer Port Functions

The Printer mode provides the user with the capability

to transfer information between an external CPU and

the 452/452PS parallel printer port. A logic 0 on chip

select pin -CSP allows the user to configure, send

data, and/or receive data via the bi-directional parallel

8-bit data bus, PD0-PD7.

Internal Registers

The 452/452PS provides 11 internal registers for

monitoring and control of the UART functions and

another 6 registers for monitoring and controlling the

printer port. These resisters are shown in Table 4

below. The UART registers function as data holding

registers (THR/RHR), interrupt status and control

registers (IER/ISR), line status and control registers

(LCR/LSR), modem status and control registers

(MCR/MSR), programmable data rate (clock) control

registers (DLL/DLM), and a user assessable

scratchpad register (SPR). The printer port registers

functions data holding registers (PR), I/O status regis-

ter (SR), I/O select register (IOSEL), and a command

and control register (COM/CON). Register functions

are more fully described in the following paragraphs.

ST16C452/452PS

Rev. 3.20

Table 4, INTERNAL REGISTER DECODE

A2 A1 A0 READ MODE WRITE MODE

General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR): Note 1*

0 0 0 Receive Holding Register Transmit Holding Register

0 0 1 Interrupt Enable Register

0 1 0 Interrupt Status Register

0 1 1 Line Control Register

1 0 0 Modem Control Register

1 0 1 Line Status Register

1 1 0 Modem Status Register

1 1 1 Scratchpad Register Scratchpad Register

Baud Rate Register Set (DLL/DLM): Note *2

0 0 0 LSB of Divisor Latch LSB of Divisor Latch

0 0 1 MSB of Divisor Latch MSB of Divisor Latch

Printer Port Set (PR/SR/IOSEL/COM/CON): Note *3

X 0 0 PORT REGISTER PORT REGISTER

X 0 1 STATUS REGISTER I/O SELECT REGISTER

X 1 0 COMMAND REGISTER CONTROL REGISTER

Note 1* The General Register set is accessible only when CS A or CS B is a logic 0.

Note 2* The Baud Rate register set is accessible only when CS A or CS B is a logic 0 and LCR bit-7 is a logic 1.

Note 3*: Printer Port Register set is accessible only when -CSP is a logic 0 in conjunction with the states of the

interface signal BIDEN and Printer Control Register bit-5 or IOSEL register.

Programmable Baud Rate Generator

The 452/452PS supports high speed modem technolo-

gies that have increased input data rates by employing

data compression schemes. For example a 33.6Kbps

modem that employs data compression may require a

115.2Kbps input data rate. A 128.0Kbps ISDN modem

that supports data compression may need an input data

rate of 460.8Kbps. The 452/452PS can support a

standard data rate of 921.6Kbps.

Single baud rate generator is provided for the transmitter

and receiver, allowing independent TX/RX channel con-

trol. The programmable Baud Rate Generator is capable

of accepting an input clock up to 24 MHz, as required

for supporting a 1.5Mbps data rate. The 452/452PS

requires that an external clock source be connected to

the CLK input pin to clock the internal baud rate

generator for standard or custom rates. (see Baud Rate

Generator Programming below).

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30

ST16C452IJ68-F

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Manufacturer:

MaxLinear

Description:

UART Interface IC DUAL UART W/PARALEL PRINTER PORT

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ST16C452IJ68-F

ST16C452IJ68-F

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