LTC2641/LTC2642
12
26412fd
For more information www.linear.com/LTC2641
OPERATION
input (SCLK). After 16 data bits have been loaded into the
serial input register, a low-to-high transition on CS trans-
fers the
data to the 16-bit DAC latch, updating the DAC
output
(see Figures 1a, 1b, 1c). While CS remains high,
the serial input shift register is disabled. If there are less
than 16 low-to-high transitions on SCLK while CS remains
low, the data will be corrupted, and must be reloaded.
Also, if there are more than 16 low-to-high transitions
on SCLK while CS remains low, only the last 16 data bits
loaded from DIN will be transferred to the DAC latch. For
the 14-bit DACs, (LTC2641-14/LTC2642-14), the MSB
remains in the same (left-justified) position in the input
16-bit data word. Therefore, two “don’t-care” bits must
be loaded after the LSB, to make up the required 16 data
bits (Figure 1b). Similarly, for the 12-bit family members
(LTC2641-12/LTC2642-12) four “don’t-care” bits must
follow the LSB (Figure 1c).
Power-On Reset
The LTC2641/LTC2642 include a power-on reset circuit
to ensure that the DAC output comes up in a known
state. When V
DD
is first applied, the power-on reset cir-
cuit sets the output of the LTC2641 to zero-scale (code
0).
The LTC2642 powers up to midscale (bipolar zero).
Depending on the DAC number of bits, the midscale code
is: 32,768 (LTC2642-16); 8,192 (LTC2642-14); or 2,048
(LTC2642-12).
Clearing the DAC
A low pulse meeting the t
9
(minimum) specification on
the CLR pin asynchronously clears the DAC latch to code
zero (LTC2641) or to midscale (LTC2642).
Figure 1c. 12-Bit Timing Diagram (LTC2641-12/LTC2642-12)
Figure 1b. 14-Bit Timing Diagram (LTC2641-14/LTC2642-14)
Figure 1a. 16-Bit Timing Diagram (LTC2641-16/LTC2642-16)
D15
MSB
1
CS
SCLK
DIN
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
D14 D13 D12 D11 D10 D9 D8
DATA (16 BITS)
D7 D6 D5 D4 D3 D2 D1 D0
DAC
UPDATED
LSB
26412 F01a
D13
MSB
1
CS
SCLK
DIN
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
D12 D11 D10 D9 D8 D7 D6
DATA (14 BITS + 2 DON’T-CARE BITS)
D5 D4 D3 D2 D1 D0 X X
DAC
UPDATED
LSB
26412 F01b
MSB
1
CS
SCLK
DIN
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
D11 D10 D9 D8 D7 D6
DATA (12 BITS + 4 DON’T-CARE BITS)
D5 D4 D3 D2 D1 D0 X X X X
DAC
UPDATED
LSB
26412 F01c
