LTC2641/LTC2642
17
26412fd
For more information www.linear.com/LTC2641
Op Amp Specifications and Bipolar DAC Accuracy
The op amp contributions to unipolar DAC error discussed
above apply equally to bipolar operation. The bipolar ap
-
plication circuit gains up the DAC span, and all errors, by
a factor of 2. Since the LSB size also doubles, the errors
in LSBs are identical in unipolar and bipolar modes.
One added error in bipolar mode comes from I
B
(IN
–
),
which flows through R
FB
to generate an offset. The full
bias current offset error becomes:
V
OFFSET
= (I
B
(IN
–
) • R
FB
– I
B
(IN
+
) • R
OUT
• 2) [Volts]
So:
VIIN kIIN k
k
V
OFFSET BB
REF
=
+
()•–()•. •
–
28 12 4
33
LSB
Settling Time with Op Amp Buffer
When using an external op amp, the output settling time
will still include the single pole settling on the LTC2641/
LTC2642 V
OUT
node, with time constant R
OUT
• (C
OUT
+
C
L
) (see Unbuffered V
OUT
Settling Time). C
L
will include
the buffer input capacitance and PC board interconnect
capacitance.
The external buffer amplifier adds another pole to the output
response, with a time constant equal to (fbandwidth/2π).
For example, assume that C
L
is maintained at the same
value as above, so that the V
OUT
node time constant is
83ns = 1μs/12. The output amplifier pole will also have a
time constant of 83ns if the closed-loop bandwidth equals
(1/2π • 83ns) = 1.9MHz. The effective time constant of
two cascaded single-pole sections is approximately the
root square sum of the individual time constants, or √2
• 83ns = 117ns, and 1/2 LSB settling time will be ~12 •
117ns = 1.4μs. This represents an ideal case, with no slew
limiting and ideal op amp phase margin. In practice, it
will take a considerably faster amplifier, as well as careful
attention to maintaining good phase margin, to approach
the unbuffered settling time of 1μs.
The output settling time
for bipolar applications (Fig-
ure
3) will be somewhat increased due to the feedback
resistor network R
FB
and R
INV
(each 28k nominal). The
parasitic capacitance, C
P
, on the op amp (–) input node
will introduce a feedback loop pole with a time constant
of (C
P
• 28k/2). A small feedback capacitor, C1, should be
included, to introduce a zero that will partially cancel this
pole. C1 should nominally be <C
P
, typically in the range
of 5pF to 10pF . This will restore the phase margin and
improve coarse settling time, but a pole-zero doublet will
unavoidably leave a slower settling tail, with a time con
-
stant of roughly (C
P
+ C1) • 28k/2, which will limit 16-bit
settling time to be greater than 2µs.
Reference and GND Input
The LTC2641/LTC2642 operates with external voltage refer
-
ences from 2
V to V
DD
, and linearity, offset and gain errors
are virtually unchanged vs V
REF
. Full 16-bit performance
can be maintained if appropriate guidelines are followed
when selecting and applying the reference. The LTC2641/
LTC2642’s very low gain error tempco of 0.1ppm/°C, typ
-
ical, corresponds
to less than 0.5LSB variation over the
–40°C to 85°C temperature range. In practice, this means
that
the overall gain error tempco will be determined almost
entirely by the external reference tempco.
The DAC voltage-switching mode “inverted” resistor lad
-
der architecture used in the LTC2641/LTC2642 exhibits a
reference
input resistance (R
REF
) that is code dependent
(see the Typical Performance curves I
REF
vs Input Code).
In unipolar mode, the minimum R
REF
is 14.8k (at code
871Chex, 34,588 decimal) and the the maximum R
REF
is
300k at code 0000hex (zero scale). The maximum change
in I
REF
for a 2.5V reference is 160µA. Since the maximum
occurs near midscale, the INL error is about one half of the
change on V
REF
, so maintaining an INL error of <0.1LSB
requires a reference load regulation of (1.53ppm • 2/160µA)
= 19 [ppm/mA]. This implies a reference output impedance
of 48mΩ, including series wiring resistance.
To prevent output glitches from occurring when resistor
ladder branches switch from GND to V
REF
, the reference
input must maintain low impedance at higher frequencies.
A 0.1μF ceramic capacitor with short leads between REF
and GND provides high frequency bypassing. A surface
mount ceramic chip capacitor is preferred because it has
the lowest inductance. An additional 1μF between
REF
and
GND provides low frequency bypassing. The circuit
APPLICATIONS INFORMATION
