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XRT91L33IG-F

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
XRT91L33
10
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT REV. V1.0.0
3.4 LVPECL Differential Input and Output DC characteristics
FIGURE 4. DIFFERENTIAL VOLTAGE SWING DEFINITIONS (INPUT OR OUTPUT) FOR CLOCK AND DATA
TABLE 7: LVPECL DIFFERENTIAL INPUTS AND OUPUTS
SYMBOL PARAMETER MIN. TYP. MAX. UNITS CONDITIONS
V
IH
Input HIGH voltage V
DD
-1.75 V
DD
-0.4 V Guaranteed input
HIGH voltage
V
IL
Input LOW voltage V
DD
-2.0 V
DD
-0.7 V Guaranteed input
LOW voltage
I
IH
Input HIGH current -0.5 10
A
V
IN DIFF
=0.5V
I
IL
Input LOW current -0.5 10 V
IN DIFF
=0.5V
V
IDIFF
Input PECL Differential Voltage, peak-
to-peak swing (see
Figure 4)
250 mV
V
OCM
Output Common-Mode Voltage 0.8 1.35 1.7 V
50 to (V
DD
-2.0V)
V
ODIFF
Output LVPECL Differential Voltage,
peak-to-peak swing (see Figure 4)
800 1700 mV
50 to (V
DD
-2.0V)
TABLE 8: LVDS OUTPUTS
SYMBOL PARAMETER MIN. TYP. MAX. UNITS CONDITIONS
V
OCM
Output common-mode voltage 1.0 1.35 1.7 V
100 between
RXDOP/N and
RXCLKP/N
V
ODIFF
Output LVDS Differential Voltage,
peak-to-peak Swing (see Figure 4)
700 1700 mV
100 between
RXDOP/N and
RXCLKP/N
μ
μA
Ω
Ω
V(+)
V(-)
0 V
2 x V
SINGLE
V
SINGLE
V
DIFF
= V(+)-V(-)
Ω
Ω
XRT91L33
11
REV. V1.0.0 STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
3.5 AC Characteristics
TABLE 9: LVTTL INPUTS
SYMBOL PARAMETER MIN. TYP. MAX. UNITS CONDITIONS
V
IH
Input HIGH voltage 2.0 V
DD
V
V
IL
Input LOW voltage 0 0.8 V
I
IH
Input HIGH current -50 50 VIN = 2.75 V, V
DD
=
Maximum
I
IL
Input LOW current -50 50 VIN = 0.5 V, V
DD
=
Maximum
TABLE 10: PERFORMANCE SPECIFICATIONS
Test Condition: VDD = 3.3V + 5% unless otherwise specified
SYMBOL PARAMETER MIN TYP MAX UNITS CONDITIONS
f VCO center frequency 622.08 MHz
f
TOL
CDR’s reference clock frequency -250 250 ppm
fT
REF_CLK
OC-12/STS-12 capture range -500 500 ppm with respect to the fixed
reference frequency
CLKOUT
DC
Clock output duty cycle 45 55 % UI 20% minimum transition
density
t
LOCK
OC-12/STS-12 acquisition lock time 16 Valid REFCK and
device already pow
-
ered up
t
LOCK_R
,
t
LOCK_F
LOCK output rise and fall time 500 ps
10% to 90%, with 100
and 5 pF capacitive
equivalent load
J
GEN_CLCK
RXCLKOP/N iitter generation 0.005 0.01 U
Irms
J
TOL
OC-12/STS-12 jitter tolerance 0.40 0.5 UI Sinusoidal input jitter of
RXDIP/N from 250 KHz
to 5MHz
μA
μA
μs
Ω
XRT91L33
12
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT REV. V1.0.0
4.0 JITTER PERFORMANCE
4.1 SONET Jitter Requirements
SONET receive equipment jitter requirements are specified jitter tolerance and jitter transfer. The definitions of
each of these types of jitter are given below.
4.1.1 Rx Jitter Tolerance:
OC-3/STM-1, and OC-12/STM-4 category II SONET interfaces should tolerate, the input jitter applied
according to the mask of
Figure 6, with the corresponding specified parameters. Jitter measurements are
done with standard SONET/SDH testers such as Acterna ANT20 as well as Agilent Omniber testers.
FIGURE 5. GR-253/G.783 JITTER TOLERANCE MASK
OC-N STM-X LEVEL
1
3
12
F0 (HZ)
10
10
10
F1 (HZ)
30
30
30
F2 (HZ)
300
300
300
F3 (HZ)
2K
6.5K
25K
F4 (HZ)
20K
65K
250K
A1 (UIPP)
0.15
0.15
0.15
A2 (UIPP)
1.5
1.5
1.5
A3 (UIPP)
15
15
15
Input
Jitter
Amplitude
(UI
pp
)
A
3
A
2
A
1
f
0
f
1
f
2
f
3
f
4
slope= -20dB/decade
slope= -20dB/decade
Jitter Frequency (Hz)
3
12
10
10
10
30
30
30
300
300
300
2K
6.5K
25K
20K
65K
250K
0.15
0.15
0.15
1.5
1.5
1.5
15
15
15
OC1/STS1 STM0
OC3/STS3 STM1
OC12/STS12 STM4
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

XRT91L33IG-F

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Buy XRT91L33IG-F
Manufacturer:
MaxLinear
Description:
Clock Generators & Support Products Recovery Unit
Lifecycle:
New from this manufacturer.
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