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XRT91L33IG-F

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
XRT91L33
7
REV. V1.0.0 STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
FIGURE 3. CONTROL DIAGRAM FOR SIGNAL DETECTION CIRCUIT AND PLL TEST OPERATION
2.6 Lock Detection
XRT91L33 features a PLL lock detection circuit. The lock detect (LOCK) output goes HIGH to indicate that the
PLL is locked to the serial data input and valid data and clock are present at the high-speed differential output.
The LOCK output will go LOW if either the LOCKTOREFN or the SIGD input is forced LOW. Additionally,
LOCK will also go low if the incoming data frequency is more than +/-500ppm away from the reference clock
frequency (REFCK x 32 in OC12 mode, REFCLK x 8 in OC3 mode). When LOCK output is driven LOW, the
VCO is forced to lock to REFCK and then released to lock on the incoming data. If the incoming data frequency
remains outside the +/-500ppm window, the training mode is repeated. Debounce logic stabilizes the LOCK
output pin to stay LOW for incoming frequencies well beyond the +/-500ppm window.
2.7 PLL Test Operation
The TEST pin is intended for use in production test and should be set at logic LOW in normal operation. If both
TEST and STS12_MODE pins are set to logic HIGH, XRT91L33 will bypass the PLL and present an inverted
version of the REFCK to the clock output RXCLKOP/N. REFCK’s rising edge is used to capture the input data
and transmit data to RXDOP/N. This bypass test operation can be used to facilitate board level debugging
process.
0
1
LOS (Internal)
SIGD
LCKTOREFN
TEST
STS12_MODE
REFCK
PLL Clock
(Internal)
RXDIP/N
22
2
RXCLKOP/N
RXDOP/N
XRT91L33
8
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT REV. V1.0.0
.
TABLE 3: SIGNAL DETECT AND PLL TEST OPERATION CONTROL
STS12_MODE TEST LCKTOREFN SIGD RXDO RXCLKO
1 0
1 1 RXDI PLL clock
1 0
1 0 Muted PLL clock
1 0
0 1 Muted PLL clock
1 0
0 0 Muted PLL clock
1 1
X X RXDI REFCK
0 0
1 1 RXDI PLL clock
0 0
1 0 Muted PLL clock
0 0
0 1 Muted PLL clock
0 0
0 0 Muted PLL clock
0 1
X X Not allowed Not allowed
XRT91L33
9
REV. V1.0.0 STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
3.0 ELECTRICAL CHARACTERISTICS
3.1 Absolute Maximum RATINGS
3.2 Operating Conditions
3.3 LVPECL Single Ended Input and Output DC characteristics
TABLE 4: ABSOLUTE MAXIMUM RATINGS
SYMBOL PARAMETER MINIMUM MAXIMUM UNIT
V
DD
Power supply voltage, referenced to GND -0.5 4.0 V
DC input voltage (LVPECL, LVTTL) -0.5 VDD+0.5 V
Output current (LVDS or LVPECL) -50 +50 mA
T
S
Storage Temperature -65 150
V
ESD
Electrostatic discharge voltage, human body model -2000 2000 V
TABLE 5: RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER MIN. TYP MAX. UNITS
V
DD
Power supply voltage 3.135 3.3 3.465 V
Temp
Operating Temperature under bias
1
1. Lower limit of specification is ambient temperature, and upper limit is case temperature.
-40 85
C
I
DD
Power supply current (outputs unterminated) 65 80 mA
P
D
Power dissipation (outputs unterminated) 215 277 mW
TABLE 6: LVPECL SINGLE ENDED INPUTS AND OUTPUTS
SYMBOL PARAMETER MIN. TYP. MAX. UNITS CONDITIONS
V
IH
Input HIGH voltage V
DD
-1.125 V
DD
-0.5 V Guaranteed input
HIGH voltage
V
IL
Input LOW voltage V
DD
-2.0 V
DD
-1.5 V Guaranteed input
LOW voltage
I
IH
Input HIGH current -0.5 10
A
V
IN
= V
DD
- 0.5V
I
IL
Input LOW current -0.5 10 V
IN
=V
DD
-2.0V
V
OL
Output LOW voltage V
DD
-2.0 V
DD
-1.8 V
50 to (V
DD
-2.0V)
V
OH
Output HIGH voltage V
DD
-1.25 V
DD
-0.67 V
50 to (V
DD
-2.0V)
°C
°
μ
μA
Ω
Ω
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

XRT91L33IG-F

Mfr. #:
Buy XRT91L33IG-F
Manufacturer:
MaxLinear
Description:
Clock Generators & Support Products Recovery Unit
Lifecycle:
New from this manufacturer.
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