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XRT91L33IG-F

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
XRT91L33
13
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
FIGURE 6. XRT91L33 JITTER TOLERANCE AT 155 MBPS OC3/STM-1
FIGURE 7. XRT91L33 JITTER TOLERANCE AT 622 MBPS OC12/STM-4
4.1.2 Jitter Generation
Maximum jitter generation is less than 0.01 UI rms within the SONET/SDH band, when rms jitter of less than
14 ps (OC-12) or 56 ps (OC-3) is presented to the serial data inputs.
0.10
1.00
10.00
100.00
0.01 0.10 1.00 10.00 100.00 1,000.00 10,000.00
Jitter
(UI)
Frequency (KHz)
XRT91L33 Jitter Tolerance OC3
Jitter
Mask
0.10
1.00
10.00
100.00
1,000.00
0.01 0.10 1.00 10.00 100.00 1,000.00 10,000.00
Jitter
(UI)
Frequency (KHz)
XRT91L33 Jitter Tolerance OC12
Jitter
Mask
XRT91L33
14
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT REV. V1.0.0
5.0 HIGH-SPEED OUTPUTS
The high-speed output buffers, RXDOP/N and RXCLKOP/N can be terminated as either LVDS or LVPECL
outputs. In LVDS mode, the transmission lines must be routed with 100
differential impedance and
terminated at the receive end with a line-to-line 100 resistor (See Figure 8).
For LVPECL conections, the transmission line must be terminated with 50 pull-down resistors near the
receiving end or an equivalent circuit. (See Figure 9)
FIGURE 8. HIGH SPEED OUTPUTS, LVDS TERMINATION
FIGURE 9. HIGH-SPEED OUTPUTS, LVPECL TERMINATION OPTIONS
Ω
Ω
XRT91L33
100 Ohm
Receiver
Ω
XRT91L33
50 Ohm50 Ohm
V
DD
– 2.0V
V
DD
– 2.0V
Receiver
XRT91L33
82 Ohm
124 Ohm
V
SS
Receiver
V
DD
V
DD
V
SS
168 Ohm168 Ohm
Creates 2V bias
when V
DD
= 3.3V
XRT91L33
168 Ohm168 Ohm
Receiver
(Baised with internal
termination)
(Unbiased and No internal
termination)
124 Ohm
82 Ohm
XRT91L33
15
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
6.0 RESAMPLED DATA AND CLOCK OUTPUTS
It is recommended that the retimed data output be captured with the rising edge of the clock output as shown in
Figure 10. Data valid time is longer for OC-3/STS-3 mode of operation than that of OC-12/STS-12. Data valid
time before the output clock’s rising edge is the available setup time (t
SU
), while the data valid time after the
clock’s rising edge is the available hold time (t
H
).
FIGURE 10. OUTPUT DATA AND CLOCK AFTER RESAMPLING
TABLE 11: OUTPUT TIMING
SYMBOL PARAMETER MINIMUM MAXIMUM UNIT CONDITION
t
SU
Available setup time 450 ps STS-12 operation (622.08 MHz)
2.0 ns STS-3 operation (155.52 MHz)
t
H
Available hold time 650 ps STS-12 operation (622.08 MHz)
3.0 ns STS-3 operation (155.52 MHz)
t
H
t
SU
RXDOP/N
RXCLKOP/N
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

XRT91L33IG-F

Mfr. #:
Buy XRT91L33IG-F
Manufacturer:
MaxLinear
Description:
Clock Generators & Support Products Recovery Unit
Lifecycle:
New from this manufacturer.
Delivery:
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