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LTC1402CGN#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
13
LTC1402
APPLICATIONS INFORMATION
WUU
U
all the internal references. When AGND2 (Pin 6) is tied to
the external ground plane, it sources 2.7mA ±30% typi-
cally; approximately 2mA are sourced through an internal
equivalent 2k resistance tied to the V
REF
(Pin 5) at 4.096V
and the remaining 0.7mA supply the internal reference
ground. The V
REF
(Pin 5) equivalent input resistance is the
same 2k tied to AGND2 (Pin 6). When you bus a common
reference voltage to several LTC1402 ADCs, you need to
keep PC board track resistance low to avoid reference
voltage attenuation at each ADC. For example, 0.5Ω of
track resistance to Pins 5 or 6 causes 0.025% of reference
voltage and input range reduction. Figure 8 shows op-
tional buffer amplifiers at each ADC to eliminate resistive
voltage drops from the common external reference to each
ADC. Figure 8 shows 10µF bypass capacitors tied to the
common analog ground plane, at V
REF
(Pin 5) and AGND2
(Pin 6), wired closely to each ADC to eliminate crosstalk of
internal ADC glitch currents from one ADC to another. The
10µF bypass capacitors are recommended whether you
drive Pins 5 and 6 with amplifiers, or with copper traces
INPUT SPAN VERSUS REFERENCE VOLTAGE
The differential input range has a voltage span that equals
the difference between the voltage at the reference buffer
output V
REF
at Pin 5, and the voltage at the reference
ground AGND2 at Pin 6. The external reference voltage
may have any value between 2V and 5V. The internal ADC
is referenced to these two points. If you use an external
reference, tie the GAIN (Pin 7) to AV
DD
(Pin 1) to disable
the internal reference, and connect the external reference
between V
REF
(Pin 5) and AGND2 (Pin 6).
If you cut the reference voltage in half by halving the gain
of the reference buffer with the GAIN (Pin 7) tied to V
REF
(Pin 5), the input span also cuts in half. In bipolar mode,
the differential input range changes from ±2.048V to
±1.024V, when the reference is cut in half. In unipolar
mode, the differential input range changes from 0V-
4.096V to 0V-2.048V, for the same reference cut in half.
Note that in both unipolar and bipolar modes, the input
range pivots around 0V with changing reference voltage.
AGND2 (Pin 6) has no direct effect on the ADC offset
voltage, it only affects input voltage span. Any external
offsetting voltages must be applied through the A
IN
+
and
A
IN
–
inputs, as shown in Figure 10b.
SEVERAL LTC1402 ADCs MAY SHARE ONE
EXTERNAL REFERENCE
Figure 8 shows how several ADCs can share a single
common external reference. The V
REF
(Pin 5) and AGND2
(Pin 6) of several LTC1402 ADCs can be tied together to
share the same external reference in a data acquisition
system. Tie GAIN (Pin 7) to AV
DD
at each ADC to disable
Figure 8. Several LTC1402 ADCs Can Share a Single
External Reference
FREQUENCY (MHz)
–40
AMPLITUDE (dB)
–30
–20
–10
0
0.1 10 100 1000
1402 F07
–50
–60
–70
1
Figure 7. CMRR vs Input Frequency
LTC1402
A
IN
+
5V
A
IN
–
V
REF
AGND2
GAIN
1402 F08
3
2
5
6
7
10µF
10µF
+
–
+
–
2
6
3
5
5V
–5V
4
1
8
7
LTC1402
A
IN
+
ANALOG
INPUTS
ANALOG
INPUTS
5V
A
IN
–
V
REF
AGND2
GAIN
3
2
5
6
7
10µF
10µF
+
–
+
–
2
6
3
5
5V
–5V
4
1
8
7
•
•
•
4.096V
1/2 LT1368CS8
1/2 LT1368CS8
1/2 LT1368CS8
1/2 LT1368CS8
0.1µF
10k
1k
5V
LT1634AI-4.096
14
LTC1402
Adjustment in Bipolar Mode with Pin 8 Held High
The code transitions occur midway between successive
integer LSB values (i.e., –FS + 0.5LSB, – FS + 1.5LSB, –FS
+ 2.5LSB,...FS – 2.5LSB, FS – 1.5LSB). The output at D
OUT
is two’s complement binary with 1LSB = FS – (–FS)/4096
= 4.096V/4096 = 1.0mV. In applications where absolute
accuracy is important, offset and full-scale errors can be
adjusted to zero. Offset error must be adjusted before full-
scale error. In Figure 10b, zero offset is achieved by
adjusting the offset applied to the A
IN
–
input. For zero
offset error, apply –0.5mV (i.e., –0.5LSB) to A
IN
+
and
adjust the offset at the A
IN
–
input using R8 until the output
code flickers between 0000 0000 0000 and 1111 1111
1111. For full-scale adjustment in Figures 10a and 10b,
apply an input voltage of 2.0465V (FS – 1.5LSB) to A
IN
+
and adjust R5 until the output code flickers between 0111
1111 1110 and 0111 1111 1111.
APPLICATIONS INFORMATION
WUU
U
more than 0.25 inch long to the common reference. You
may also choose to tie AGND2 (Pin 6) directly to a solid
analog ground plane and eliminate all the 10µF capacitors
at this pin. The external reference source needs to have
enough output drive current for the 2kΩ load at each ADC.
FULL-SCALE AND OFFSET ADJUSTMENT
Figure 9 shows the ideal input/output characteristics for
the LTC1402 in bipolar mode and unipolar mode. Figure
10a shows the components required for full-scale error
adjustment. Figure 10b includes the components for off-
set and full-scale adjustment.
Figure 9. LTC1402 Transfer Characteristic
Figure 10a. Full-Scale Adjustment Circuit with
±10LSB Range
Figure 10b. Offset and Full-Scale Adjustment
Circuits with ±10LSB Range
Adjustment in Unipolar Mode with Pin 8 Held Low
The code transitions occur midway between successive
integer LSB values (i.e., –FS + 0.5LSB, –FS + 1.5LSB,
–FS + 2.5LSB,...FS – 2.5LSB, FS – 1.5LSB). The output at
D
OUT
is binary with 1LSB = FS/4096 = 4.096V/4096 =
1.0mV. In applications where absolute accuracy is impor-
tant, offset and full-scale errors can be adjusted to zero.
Offset error must be adjusted before full-scale error. In
Figure 10b, zero offset is achieved by adjusting the offset
applied to the A
IN
–
input. For zero offset error apply
–0.5mV (i.e., –0.5LSB) to A
IN
+
and adjust the offset at the
A
IN
–
input using R8 until the output code flickers between
INPUT VOLTAGE (V)
BIPOLAR OUTPUT CODE
UNIPOLAR OUTPUT CODE
1402 F09
011...111
011...110
011...101
100...000
100...001
100...010
111...111
111...110
111...101
000...000
000...001
000...010
FS – 1LSB–(FS – 1LSB)
64k
R1
51Ω
R3
51Ω
64k
REFERENCE
AMP
S/H
10µF
R4
470k
R2
24k
R7
7.5k
R5
500Ω
GAIN
V
REF
5
5V
5V
ANALOG INPUT
0V TO 4.096V
OR ±2.048V
OFFSET
ADJ
FULL-SCALE
ADJ
7
A
IN
–
4
A
IN
+
3
AGND26
LTC1402
2.048V
1402 F010b
R8
10k
R6
24k
BANGAP
REFERENCE
64k
R1
51Ω
R3
51Ω
64k
10µF
R4
470k
R2
39k
R5
500Ω
GAIN
V
REF
5
ANALOG INPUT
0V TO 4.096V
OR ±2.048V
7
A
IN
–
4
A
IN
+
3
AGND26
LTC1402
2.048V
1402 F010a
BANGAP
REFERENCE
REFERENCE
AMP
S/H
15
LTC1402
APPLICATIONS INFORMATION
WUU
U
0000 0000 0000 and 0000 0000 0001. For full-scale ad-
justment in Figures 10a and 10b, apply an input voltage of
2.0465V (FS – 1.5LSBs) to A
IN
+
and adjust R5 until the
output code flickers between 1111 1111 1110 and 1111
1111 1111.
BOARD LAYOUT AND BYPASSING
Wire wrap boards are not recommended for high resolu-
tion and/or high speed A/D converters. To obtain the best
performance from the LTC1402, a printed circuit board
with ground plane is required. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 2 (AGND1), Pin 6 (AGND2), Pin 13 (DGND) and all
other analog grounds should be connected directly to an
analog ground plane. Pin 9 (OGND) should be connected
near Pin13 (DGND), where the analog ground plane ties to
the logic system ground. The V
REF
bypass capacitor and
the DV
DD
bypass capacitor should also be connected to
this analog ground plane, see Figure 11. No other digital
grounds should be connected to this analog ground plane.
Low impedance analog and digital power supply common
returns are essential to low noise operation of the ADC and
the foil width for these tracks should be as wide as
possible. The traces connecting the pins and bypass
capacitors must be kept short and should be made as wide
as possible.
The LTC1402 has differential inputs to minimize noise
coupling. Common mode noise on the A
IN
+
and A
IN
–
leads
will be rejected by the input CMRR. The A
IN
–
input can be
used as a ground sense for the A
IN
+
input; the LTC1402 will
hold and convert the difference voltage between A
IN
+
and
A
IN
–
. The leads to A
IN
+
(Pin 3) and A
IN
–
(Pin 4) should be
kept as short as possible. In applications where this is not
possible, the A
IN
+
and A
IN
–
traces should be run side-by-
side to cancel noise coupling.
SUPPLY BYPASSING
High quality, low series resistance 10µF ceramic bypass
capacitors should be used at the V
DD
and V
REF
pins.
Surface mount ceramic capacitors such as Murata
GRM235Y5V106Z016 provide excellent bypassing in a
small board space. Alternatively, 10µF tantalum capaci-
tors in parallel with 0.1µF ceramic capacitors can be used.
Bypass capacitors must be located as close to the pins as
possible. The traces connecting the pins and the bypass
capacitors must be kept short and should be made as wide
as possible.
POWER-DOWN MODES
Upon power-up, the LTC1402 is initialized to the active
state and is ready for conversion. The Nap and Sleep Mode
waveforms show the power-down modes for the LTC1402.
The SCK and CONV inputs control the power-down modes
(see Timing Diagrams). Two rising edges at CONV, with-
out any intervening rising edges at SCK, put the LTC1402
in Nap mode and the power drain drops from 90mW to
Figure 11. Power Supply Grounding Practice
1402 F11
A
IN
+
AGND2 AGND1V
REF
AV
DD
DV
DD
OV
DD
D
OUT
OGND
LTC1402
DIGITAL
SYSTEM
SYSTEM
GROUND
10µF10µF
ANALOG
INPUT
CIRCUITRY
6145
4
11213 9
10
12
3V TO 5V
DGND
3
A
IN
–
V
SS
2
ANALOG GROUND PLANE
10µF
+
–
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LTC1402CGN#TRPBF

Mfr. #:
Buy LTC1402CGN#TRPBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Serial 12-B, 2.2Msps Smpl ADC w/ SD
Lifecycle:
New from this manufacturer.
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