4
LTC1402
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
SAMPLE(MAX)
Maximum Sampling Frequency (Conversion Rate) ● 2.2 MHz
t
THROUGHPUT
Minimum Sampling Period (Conversion + Acquisiton Period) ● 455 ns
t
SCK
Minimum Clock Period ● 28 10000 ns
t
CONV
Conversion Time (Note 9) 14 SCK cycles
t
0
14th SCLK↑ to CONV↑ Interval (Notes 9, 10, 16) ● 57 ns
t
1
Minimum Positive or Negative SCK Pulse Width (Note 9) ● 3.8 6 ns
t
2
CONV to SCK Setup Time (Notes 9, 13) ● 7.3 12 ns
t
3
SCK After CONV (Note 9) ● 0ns
t
4
Minimum Positive or Negative CONV Pulse Width (Note 9) ● 3.5 5 ns
t
5
SCK to Sample Mode (Note 9) ● 914 ns
t
6
CONV to Hold Mode (Notes 9, 14) ● 3.4 5 ns
t
7
Minimum Delay Between Conversions (Note 9) ● 48 ns
t
8
Minimum Delay from SCK to Valid Bits 0 Through 11 (Notes 9, 15) ● 912 ns
t
8a
Minimum Delay from SCK to Valid REFREADY (Notes 9, 15) ● 15 20 ns
t
9
SCK to Hi-Z at D
OUT
(Notes 9, 15) ● 11.4 16 ns
t
10
Previous D
OUT
Bit Remains Valid After SCK (Notes 9, 15) ● 47 ns
t
11
REFREADY Bit Delay After Sleep-to-Wake Transition (Notes 9, 17) ● 10 ms
t
12
V
REF
Settling Time After Sleep-to-Wake Transition (Notes 9, 17) ● 2ms
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 5)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
DD
Positive Supply Voltage 4.75 5.25 V
V
SS
Negative Supply Voltage –5.25 0 V
I
DD
Positive Supply Current Active Mode ● 18 30 mA
Nap Mode
● 35 mA
Sleep Mode 2 10 µA
I
SS
Negative Supply Current Active, Sleep or Nap Modes with SCK Off ● 2 µA
PD Power Dissipation Active Mode with SCK in Fixed State (Hi or Lo) 90 150 mW
POWER REQUIRE E TS
WU
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, AGND1
and AGND2 wired together.
Note 3: When these pins are taken below V
SS
or above V
DD
, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below V
SS
or greater than V
DD
without latchup.
Note 4: When these pins are taken below V
SS
, they will be clamped by
internal diodes. This product can handle input currents greater than
100mA below V
SS
or greater than V
DD
. These pins are not clamped to V
DD
.
Note 5: V
DD
= 5V, f
SAMPLE
= 2.2MHz, V
SS
= 0V for unipolar mode
specifications and V
SS
= –5V for bipolar specifications.
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 5)
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended A
IN
+
input with A
IN
–
grounded and using the internal reference in
bipolar mode with ±5V supplies.
Note 7: Integral linearity is defined as the deviation of a code from the
straight line passing through the actual endpoints of a transfer curve. The
deviation is measured from the center of quantization band.
Note 8: Bipolar offset is the offset measured from –0.5LSB when the input
flickers between 1000 0000 0000 and 0111 1111 1111.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The analog input range is defined as the voltage difference
between A
IN
+
and A
IN
–
. The bipolar ±2.048V input range could be used
with a single 5V supply if the absolute voltages of the inputs remain within
the single 5V supply voltage.
TI I G CHARACTERISTICS
UW
