8
LTC1402
GAIN (Pin 7): Tie to AGND2 to set the reference voltage to
4.096V or tie to V
REF
to set the reference voltage to 2.048V.
(Note 4)
BIP/UNI (Pin 8): Tie to logic low to set the input range to
unipolar mode or tie to logic high to set the input range to
bipolar mode. (Note 4)
OGND (Pin 9): Output Ground for the Output Driver. This
pin can be tied to the digital ground of the system. All other
ground pins should be tied to the analog ground plane.
D
OUT
(Pin 10): Three-State Data Output. (Note 3) Each
output data word represents the analog input at the start
of the previous conversion.
OV
DD
(Pin 11): Output Data Driver Power. Tie to V
DD
when
driving 5V logic. Tie to 3V when driving 3V logic.
DV
DD
(Pin 12): Digital Power for Internal Logic. Bypass to
DGND with 10µF ceramic (or 10µF tantalum in parallel with
0.1µF ceramic).
PIN FUNCTIONS
UUU
DGND (Pin 13): Digital Ground for Internal Logic. Tie to
solid analog ground plane.
V
SS
(Pin 14): Negative Supply Voltage. Bypass to solid
analog ground plane with 10µF ceramic (or 10µF tantalum
in parallel with 0.1µF ceramic) or tie directly to the solid
analog ground plane for single supply use. Must be set
more negative than either A
IN
+
or A
IN
–
. Set to 0V or –5V.
SCK (Pin 15): External Clock. Advances the conversion
process and sequences the output data at D
OUT
on the
rising edge. Responds to 5V or 3V CMOS and to TTL levels.
(Note 4). One or more pulses wake from Nap or Sleep.
CONV (Pin 16): Holds the input analog signal and starts
the conversion on the rising edge. Responds to 5V or 3V
CMOS and to TTL levels. (Note 4). Two pulses with SCK in
fixed high or fixed low state start Nap Mode. Four pulses
with SCK in fixed high or fixed low state start Sleep mode.
BLOCK DIAGRA
W
12-BIT CAPACITIVE DAC
COMPREF AMP
+
–
2.048V REF
64k
GAIN
C
SAMPLE
C
SAMPLE
CONTROL LOGIC
SCKCONV
16 15
INTERNAL
CLOCK
OUTPUT
DRIVER
ZEROING SWITCHES
AV
DD
1
12
DV
DD
14
8
10
11
9
V
SS
BIP/UNI
OV
DD
D
OUT
OGND
A
IN
+
3
4
7
5
6
2
13
A
IN
–
AGND1
AGND2
V
REF
DGND
1402 BD
+
–
SUCCESSIVE APPROXIMATION
REGISTER
64k
