13
IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™
256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
the Read Enable 2 (REN2) control input can be grounded (see Figure 14). In
this configuration, the Write Enable 2/Load (WEN2/LD) pin is set LOW at Reset
so that the pin operates as a control to load and read the programmable flag
offsets.
Figure 15. Block Diagram of 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 and 8,192 x 18
Synchronous FIFO Used in a Width Expansion Configuration
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION
A single IDT72V201/72V211/72V221/72V231/72V241/72V251 may be
used when the application requirements are for 256/512/1,024/2,048/4,096/
8,192 words or less. When these FIFOs are in a Single Device Configuration,
1,024/2,048/4,096/8,192 words. The existence of two enable pins on the read
and write port allow depth expansion. The Write Enable 2/Load pin is used as
a second write enable in a depth expansion configuration thus the program-
mable flags are set to the default values. Depth expansion is possible by using
one enable input for system control while the other enable input is controlled by
expansion logic to direct the flow of data. A typical application would have the
expansion logic alternate data access from one device to the next in a sequential
manner. These FIFOs operate in the Depth Expansion configuration when the
following conditions are met:
1. The WEN2/ LD pin is held HIGH during Reset so that this pin
operates a second Write Enable.
2. External logic is used to control the flow of data.
Please see the Application Note" DEPTH EXPANSION OF IDT'S SYN-
CHRONOUS FIFOs USING THE RING COUNTER APPROACH" for details
of this configuration.
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting the corresponding input
controls signals of multiple devices. A composite flag should be created for each
of the end-point status flags (EF and FF). The partial status flags (AE and AF)
can be detected from any one device. Figure 15 demonstrates a 18-bit word
width by using two IDT72V201/72V211/72V221/72V231/72V241/72V251s.
Any word width can be attained by adding additional IDT72V201/72V211/
72V221/72V231/72V241/72V251s.
When these devices are in a Width Expansion Configuration, the Read
Enable 2 (REN2) control input can be grounded (see Figure 15). In this
configuration, the Write Enable 2/Load (WEN2/LD) pin is set LOW at Reset so
that the pin operates as a control to load and read the programmable flag offsets.
DEPTH EXPANSION
The IDT72V201/72V211/72V221/72V231/72V241/72V251 can be
adapted to applications when the requirements are for greater than 256/512/
Figure 14. Block Diagram of Single 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 Synchronous FIFO
DATA OUT (Q
0
- Q
8
)
DATA IN (D
0
- D
8
)
RESET (RS)
READ CLOCK (RCLK)
READ ENABLE 1 (REN1)
OUTPUT ENABLE (OE)
EMPTY FLAG (EF)
PROGRAMMABLE ALMOST-EMPTY (PAE)
READ ENABLE 2 (REN2)
WRITE CLOCK (WCLK)
WRITE ENABLE 1 (WEN1)
WRITE ENABLE 2/LOAD (WEN2/LD)
FULL FLAG (FF)
PROGRAMMABLE ALMOST-FULL (PAF)
IDT
72V201
72V211
72V221
72V231
72V241
72V251
4092 drw16
DATA IN (D)
WRITE CLOCK (WCLK)
18 9 9
RESET (RS)
READ CLOCK (RCLK)
DATA OUT (Q)
9
18
READ ENABLE 2 (REN2)READ ENABLE 2 (REN2)
WRITE ENABLE1 (WEN1)
FULL FLAG (FF) #1
PROGRAMMABLE (PAF)
PROGRAMMABLE (PAE)
EMPTY FLAG (EF) #2
OUTPUT ENABLE (OE)
READ ENABLE1 (REN1)
9
WRITE ENABLE2/LOAD (WEN2/LD)
FULL FLAG (FF) #2
EMPTY FLAG (EF) #1
RESET (RS)
4092 drw17
IDT
72V201
72V211
72V221
72V231
72V241
72V251
IDT
72V201
72V211
72V221
72V231
72V241
72V251
