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ADV7127KRU50-REEL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
ADV7127 Data Sheet
Rev. A | Page 6 of 18
3.3 V TIMING SPECIFICATIONS
V
AA
= 3.0 V to 3.6 V,
1
V
REF
= 1.235 V, R
SET
= 560 Ω. All specifications T
MIN
to T
MAX
,
2
unless otherwise noted. T
J MAX
= 110°C.
Table 4.
Parameter
3
Symbol Min Typ Max Unit Test Conditions/Comments
ANALOG OUTPUTS
Delay t
6
7.5 ns
Rise/Fall Time
4
t
7
1.0 ns
Transition Time
5
t
8
15 ns
Skew
6
t
9
1 2 ns Not shown in Figure 2
CLOCK CONTROL
7
f
CLK
50 MHz 50 MHz grade
140 MHz 140 MHz grade
240
MHz
240 MHz grade
Data and Control
Setup
6
t
1
1.5 ns
Hold
6
t
2
2.5 ns
Clock Period
6
t
3
2.5 ns f
MAX
= 240 MHz
Clock Pulse Width
High t
4
1.1 ns f
MAX
= 240 MHz
t
4
6
2.85 ns f
MAX
= 140 MHz
t
4
6
8.0 ns f
MAX
= 50 MHz
Low
6
t
5
1.4 ns f
MAX
= 240 MHz
t
5
2.85 ns f
MAX
= 140 MHz
t
5
8.0 ns f
MAX
= 50 MHz
Pipeline Delay
6
t
PD
1.0 1.0 1.0 Clock cycles Not shown in Figure 2
Up Time
PSAVE
6
t
10
4 10 ns Not shown in Figure 2
PDOWN
t
11
320 ns Not shown in Figure 2
1
The values stated in Table 4 were obtained using V
AA
in the range of 3.0 V to 3.6 V.
2
Temperature range: T
MIN
to T
MAX
: −40°C to +85°C at 50 MHz and 140 MHz, and 0°C to 70°C at 240 MHz.
3
Timing specifications are measured with input levels of 3.0 V (V
IH
) and 0 V (V
IL
) for both 5 V and 3.3 V supplies.
4
Rise time was measured from the 10% to 90% point of zero to full-scale transition, and fall time from the 90% to 10% point of a full-scale transition.
5
Measured from 50% point of full-scale transition to 2% of final value.
6
Guaranteed by characterization.
7
f
CLK
maximum specification production tested at 125 MHz and 3.3 V. Limits specified in Table 4 are guaranteed by characterization.
CLOCK
DATA
t
4
t
5
t
7
t
8
NOTES
1. OUTPUT DELAY (
t
6
) MEASURED FROM THE 50% POINT OF THE RISING
EDGE OF CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION.
2. OUTPUT RISE/FALL TIME (t
7
) MEASURED BETWEEN THE 10% AND
90% POINTS OF FULL-SCALE TRANSITION.
3. TRANSITION TIME (t
8
) MEASURED FROM THE 50% POINT OF FULL-SCALE
TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE.
t
2
DIGITAL INPUTS
D9 TO D0
t
3
t
1
t
6
ANALOG OUTPUTS
I
OUT
, I
OUT
14959-002
Figure 2. Timing Diagram
Data Sheet ADV7127
Rev. A | Page 7 of 18
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
V
AA
to GND 7 V
Voltage on Any Digital Pin
GND − 0.5 V to V
AA
+ 0.5 V
Ambient Operating Temperature Range
(T
A
)
−40°C to +85°C
Storage Temperature Range(T
S
) −65°C to +150°C
Junction Temperature (T
J
) 150°C
Lead Temperature (Soldering, 10 sec) 300°C
Vapor Phase Soldering (1 Minute)
220°C
I
OUT
to GND
1
0 V to V
AA
1
Analog output short circuit to any power supply or common can be of an
indefinite duration.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
ADV7127 Data Sheet
Rev. A | Page 8 of 18
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
DNC
CLOCK
GND
GND
V
AA
D0
PSAVE
R
SET
V
REF
I
OUT
COMP
I
OUT
DNC
PDOWN
D8
D7
D6
V
AA
D1
D2
D5
D4
D3
D9
14959-003
1
2
3
4
5
6
7
8
9
10
20
21
22
23
24
19
18
17
16
15
14
1312
11
DNC = DO NOT CONNECT
ADV7127
(Not to Scale)
TOP VIEW
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1 to 9,
24
D0 to D9
Data Inputs (TTL-Compatible). Data is latched on the rising edge of CLOCK. D0 is the least significant data bit.
Unused data inputs are connected to either the regular printed circuit board (PCB) power or ground plane. Data
inputs are red, green, or blue pixel inputs.
10, 17 V
AA
Analog Power Supply (5 V ± 5%). All V
AA
pins on the ADV7127 must be connected.
11
PDOWN
Power-Down Control Pin. The ADV7127 completely powers down, including the voltage reference circuit, when
PDOWN
is low.
12, 13 DNC Do Not Connect. Do not connect to these pins.
14 CLOCK
Clock Input (TTL-Compatible). The rising edge of CLOCK latches D0 to D9 where D0 to D9 can be red, green, or
blue pixel data inputs (TTL-compatible). CLOCK is typically the pixel clock rate of the video system. CLOCK is driven
by a dedicated TTL buffer.
15, 16 GND Ground. All GND pins must be connected.
18
I
OUT
Differential Current Output. This pin is capable of directly driving a doubly terminated 75 Ω load. If not required,
this output is tied to ground.
19 I
OUT
Current Output. This high impedance current source is capable of directly driving a doubly terminated 75 Ω coaxial
cable.
20 COMP
Compensation Pin. COMP is a compensation pin for the internal reference amplifier. A 0.1 μF ceramic capacitor
must be connected between COMP and V
AA
.
21 V
REF
Voltage Reference Input. An external 1.23 V voltage reference must be connected to this pin. The use of an external
resistor divider network is not recommended. A 0.1 μF decoupling ceramic capacitor is connected between V
REF
and V
AA
.
22 R
SET
Full-Scale Adjust Control. A resistor (R
SET
) connected between this pin and GND controls the magnitude of the full-
scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current. The
relationship between R
SET
and the full-scale output current on I
OUT
is given by I
OUT
(mA) = 7968 × V
REF
(V)/R
SET
(Ω).
23
PSAVE
Power Save Control Pin. The device is put into standby mode when PSAVE is low. The internal voltage reference
circuit is still active.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

ADV7127KRU50-REEL

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Buy ADV7127KRU50-REEL
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC CMOS 240 MHz 10B High Speed DAC
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