Operation M41T01
10/24 DocID025389 Rev 2
2.2 READ mode
In this mode, the master reads the M41T01 slave after setting the slave address (see
Figure 6). Following the WRITE mode control bit (R/W = 0) and the acknowledge bit, the
word address An is written to the on-chip address pointer. Next the START condition and
slave address are repeated, followed by the READ mode control bit (R/W = 1). At this point,
the master transmitter becomes the master receiver. The data byte which was addressed
will be transmitted and the master receiver will send an acknowledge bit to the slave
transmitter. The address pointer is only incremented on reception of an acknowledge bit.
The M41T01 slave transmitter will now place the data byte at address A
n+1
on the bus. The
master receiver reads and acknowledges the new byte and the address pointer is
incremented to A
n+2
.
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
An alternate READ mode may also be implemented, whereby the master reads the M41T01
slave without first writing to the (volatile) address pointer. The first address that is read is the
last one stored in the pointer (see Figure 7 on page 11).
Figure 6. Slave address location
AI00602
R/W
SLAVE ADDRESS
START A
0100011
MSB
LSB
DocID025389 Rev 2 11/24
M41T01 Operation
24
Figure 7. READ mode sequence
Figure 8. Alternate READ mode sequence
AI00899
BUS ACTIVITY:
ACK
S
ACK
ACK
ACK
NO ACK
STOP
START
P
SDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n DATA n+1
DATA n+X
WORD
ADDRESS (An)
SLAVE
ADDRESS
S
START
R/W
SLAVE
ADDRESS
ACK
AI00895
BUS ACTIVITY:
ACK
S
ACK
ACK
ACK
NO ACK
STOP
START
PSDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n DATA n+1 DATA n+X
SLAVE
ADDRESS
Operation M41T01
12/24 DocID025389 Rev 2
2.3 WRITE mode
In this mode the master transmitter transmits to the M41T01 slave receiver. Bus protocol is
shown in Figure 9. Following the START condition and slave address, a logic '0' (R/W = 0) is
placed on the bus and indicates to the addressed device that word address An will follow
and is to be written to the on-chip address pointer. The data word to be written to the
memory is strobed in next and the internal address pointer is incremented to the next
memory location within the RAM on the reception of an acknowledge clock. The M41T01
slave receiver will send an acknowledge clock to the master transmitter after it has received
the slave address and again after it has received the word address and each data byte (see
Figure 6 on page 10).
2.4 Data retention mode
With valid V
CC
applied, the M41T01 can be accessed as described above with READ or
WRITE Cycles. Should the supply voltage decay, the M41T01 will automatically deselect,
write protecting itself when V
CC
falls (see Figure 13 on page 20).
Figure 9. WRITE mode sequence
AI00591
BUS ACTIVITY:
ACK
S
ACK
ACK
ACK
ACK
STOP
START
PSDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n DATA n+1 DATA n+X
WORD
ADDRESS (An)
SLAVE
ADDRESS

M41T01M6F

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Real Time Clock Low-Pwr serial RTC W/ battry switchover
Lifecycle:
New from this manufacturer.
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