DocID025389 Rev 2 7/24
M41T01 Operation
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2 Operation
The M41T01 clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 8 bytes
contained in the device can then be accessed sequentially in the following order:
1. Seconds register
2. Minutes register
3. Century/hours register
4. Day register
5. Date register
6. Month register
7. Years register
8. Control register
The M41T01 clock continually monitors V
CC
for an out of tolerance condition. Should V
CC
fall below V
SO
, the device terminates an access in progress and resets the device address
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from an out of tolerance system. When V
CC
falls below V
SO
,
the device automatically switches over to the battery and powers down into an ultra low
current mode of operation to conserve battery life. Upon power-up, the device switches from
battery to V
CC
at V
SO
and recognizes inputs.
2.1 2-wire bus characteristics
This bus is intended for communication between different ICs. It consists of two lines: one
bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and the
SCL lines must be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is high.
Changes in the data line while the clock line is high will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
Bus not busy
Both data and clock lines remain high.
Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines
the START condition.
Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines
the STOP condition.
