8545AGI-02 REVISION A 5/7/15 2 ©2015 Integrated Device Technology, Inc.
8545I-02 Data Sheet LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1, 9, 13 GND Power Power supply ground.
2 CLK_EN Input Pullup
Synchronizing clock enable. When HIGH, clock outputs follows clock input. When
LOW, Qx outputs are forced low, nQx outputs are forced high.
LVCMOS / LVTTL interface levels.
3 CLK_SEL Input Pulldown
Clock select input. When HIGH, selects CLK2 input.
When LOW, selects CLK1 input. LVCMOS / LVTTL interface levels.
4 CLK1 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
5, 7 nc Unused No connect.
6 CLK2 Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
8 OE Input Pullup
Output enable. Controls enabling and disabling of outputs Q0/nQ0 through
Q3/nQ3. LVCMOS/LVTTL interface levels.
10, 18 V
DD
Power Positive supply pins.
11, 12 nQ3, Q3 Output Differential output pair. LVDS interface levels.
14, 15 nQ2, Q2 Output Differential output pair. LVDS interface levels.
16, 17 nQ1, Q1 Output Differential output pair. LVDS interface levels.
19, 20 nQ0, Q0 Output Differential output pair. LVDS interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
