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8545AGI-02LF

P1-P3P4-P6P7-P9P10-P12P13-P13
8545AGI-02 REVISION A 5/7/15 4 ©2015 Integrated Device Technology, Inc.
8545I-02 Data Sheet LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Table 4B. LVCMOS/LVTTL DC Characteristics, V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Table 4C. LVDS DC Characteristics, V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
Item Rating
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, I
O
Continuos Current
Surge Current
10mA
15mA
Package Thermal Impedance,
JA
91.1C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Positive Supply Voltage 3.135 3.3 3.465 V
I
DD
Power Supply Current 90 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage 2 V
DD
+ 0.3 V
V
IL
Input Low Voltage -0.3 0.8 V
I
IH
Input
High Current
CLK1, CLK2, CLK_SEL V
DD
= V
IN
= 3.465V 150 µA
OE, CLK_EN V
DD
= V
IN
= 3.465V 5 µA
I
IL
Input
Low Current
CLK1, CLK2, CLK_SEL V
DD
= 3.465V, V
IN
= 0V -5 µA
OE, CLK_EN V
DD
= 3.465V, V
IN
= 0V -150 µA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OD
Differential Output Voltage 275 525 mV
V
OD
V
OD
Magnitude Change 50 mV
V
OS
Offset Voltage 1.1 1.25 1.4 V
V
OS
V
OS
Magnitude Change 5 50 mV
8545AGI-02 REVISION A 5/7/15 5 ©2015 Integrated Device Technology, Inc.
8545I-02 Data Sheet LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
AC Electrical Characteristics
Table 5. AC Characteristics, V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Measured using 50% duty cycle.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 350 MHz
t
PD
Propagation Delay; NOTE 1 1.0 1.45 ns
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
155.52MHz, Integration Range:
12kHz – 20MHz
0.14 ps
tsk(o) Output Skew; NOTE 2, 4 60 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4 450 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 150 700 ps
odc Output Duty Cycle; NOTE 5
ƒ 166MHz 45 55 %
ƒ > 166MHz 40 60 %
8545AGI-02 REVISION A 5/7/15 6 ©2015 Integrated Device Technology, Inc.
8545I-02 Data Sheet LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
Additive Phase Jitter @ 155.52MHz
12kHz to 20MHz = 0.14ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
P1-P3P4-P6P7-P9P10-P12P13-P13

8545AGI-02LF

Mfr. #:
Buy 8545AGI-02LF
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 4 LVDS OUT BUFFER
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