Si4356
10 Rev 1.2
Figure 2 shows the application circuit for a particular radio configuration (433.92 MHz, OOK, 2 kbps, 206 kHz
RxBW) with all optional connections. See Sections 5 and 7 for Si4356 pin functionality.
Figure 2. Si4356 Application Circuit Example
Note:
1. R1 is required to minimize power up current. R1 is only necessary for pin configurations where SEL2 or SEL3 is
mapped to GND.
2. An optional external low-pass RC filter may be connected to RX_DATA to filter the output and improve sensitivity.
R2 and C7 should be selected to realize a cut-off frequency that is ~40% larger than that targeted data rate
according to f
c
= 1/(2RC).
30 MHz
L1
GND
SEL0
19
18
17
16
1
2
3
4
15
14
13
7
8
9
10
SEL1
RX_DATA/OUT1
2
STBY
RXn
RST
RXp
XIN
SEL3
GND
XOUT
5
NC
6 20
SEL2
11
12
C2
Si4356
MSTAT/OUT0
VDD
100 nF
C5
100 pF
C4
1 μF
L2
C3
C6
MCU
Data In
Rx STBY (Optional)
Clock In (Optional)
VDD
Reset (Optional)
Mode Status (Optional)
C1
270 pF
2.7 pF
5.1 pF
56 nH
56 nH
10 k:
R1
1
GND
VDD
VDD
GND
CLK_OUT
R2
C7
Optional RC Filter
2
Si4356
Rev 1.2 11
3. Device Configuration
The Si4356 is configured for operation using the four configuration selector pins (SEL0 – SEL3). These pins will be
connected to one of four possible inputs: GND, VDD, RX DATA/OUT1 (pin 14), or OUT0 (pin 12). Refer to the
tables below for how these pins should be connected for the desired configuration.
SEL0 and SEL1 may be connected to VDD, GND, or OUT1 to choose desired frequency. Note that a 10 k
resistor should be inserted between SEL1 and OUT1 when SEL1 is mapped to OUT1. See Table 9 for frequency
settings.
SEL2 and SEL3 may be connected to VDD, GND, or OUT1 to choose desired modem configuration. See Table 10
for basic configurations. Note that a 10 k
resistor should inserted between SEL2 and/or SEL3 and GND when
SEL2 and/or SEL3 are mapped to GND.
Table 9. Frequency Selection
SEL0 SEL1 Frequency (MHz)
GND VDD 433.92
VDD VDD 315.00
OUT1 VDD 434.15
GND OUT1 867.84
VDD OUT1 868.30
OUT1 OUT1 917.00
Table 10. Basic Configuration
Config.
Name
SEL2 SEL3 Mod Data Rate
(kbps)
RxBW (kHz) Squelch Recommended
F
DEV
(kHz)
OOK1 GND GND OOK 0.5–5 206 Disabled
OOK2 VDD GND OOK 1–10 370 Disabled
OOK3 OUT1 GND OOK 10–50 370 Disabled
OOK4 OUT0 GND OOK 50–120 370 Disabled
OOK5 GND VDD OOK 50–120 535 Disabled
OOK6 VDD VDD OOK 0.5–2.4 100 Disabled
FSK1 GND OUT1 (G)FSK 0.5–30 155 Disabled 30
FSK2 VDD OUT1 (G)FSK 0.5–30 185 Disabled 70
FSK3 OUT1 OUT1 (G)FSK 0.5–30 275 Disabled 30
FSK4 OUT0 OUT1 (G)FSK 10–120 275 Disabled 70
FSK5 GND OUT0 (G)FSK 10–120 535 Disabled 70
FSK6 VDD OUT0 (G)FSK 0.5–2.4 155 Enabled 30
FSK7 OUT1 OUT0 (G)FSK 0.5–2.4 275 Enabled 30
Si4356
12 Rev 1.2
To disable the system clock, connect CLK_OUT to OUT0. Otherwise, CLK_OUT is enabled. See Table 11 settings.
Table 11. System Clock
CLK_OUT (Pin 10) Clock Output
OUT0 OFF
XON

SI4356-B1A-FMR

Mfr. #:
Manufacturer:
Silicon Labs
Description:
RF Receiver RX sub-GHz receiver
Lifecycle:
New from this manufacturer.
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